iosr-JEEE   Volume-8 ~ Issue-2

Abstract: Photovoltaic (PV) power systems have been widely applied in commercial and domestic facilities. Electrical Energy Storage (EES) systems are mandatory in standalone PV systems for continuous power supply. In this paper the efficiency and robustness enhancement methods for PV systems under partial shading have been investigated. Partial shading due to moving clouds and shadows of nearby obstacles on the PV module array causes significant efficiency degradation, since shaded and non-shaded PV modules have large discrepancy in their maximum power points. Use of by-pass diodes for each PV module may mitigate the negative effect from partial shading. However, this method alone may still face severe energy efficiency degradation caused by the energy loss due to parasitic effects in the EES elements under variable incoming power from the PV modules. Hence, this paper investigates the effect of shading on photovoltaic cells.

[1] J. Perlin. From Space To Earth (The Story Of Solar Electricity). Harvard University Press: London, 1999.
[2] Solar Energy Technologies and Applications, CANREN: www.canren.gc.ca/techappl/index.asp?caid=5&pgid=121, Sept. 4th, 2011
[3] G. John. Photovoltaics: Solar Electricity and Solar Cells in Theory and Practice.Internet: http://www.solarserver.com, Oct. 21, 2011
[4] K. Gil, (2004) "How do Photovoltaic Work?" Science News.1 (1), p 4. [5] L. David. "Handbook of Batteries". McGraw-Hill: New York, 2002.
[6] "Wiring solar panels". Internet: www.solar-facts.com/wiring solar panels, Dec. 5, 2011
[7] "How charge controllers work". Internet: www.altestore.com/charge-controllers/c432
[8] "Solarregulators".Internet:www.enegrymatters.com/au/renewableenergy/solarregulator/charge-controller, Aug. 17th, 2011.
[9] "Inverters". Internet: www.en/wikipedia.org/wiki/inverter_(electrical), Jun.1, 2011. [10] J. Mervin et al. Contemporary Energy Issues Grid-Connected Solar Electronics.Department of Electrical Engineering and Computer Sciences.EE-290N-3; University of California, 2002.

Abstract: Use of by-pass diodes for each PV module may mitigate the negative effect from partial shading. However, this method alone may still face severe energy efficiency degradation caused by the energy loss due to parasitic effects in the EES elements under variable incoming power from the PV modules. Hence, this paper proposes methods to enhance the PV system efficiency and robustness under partial shading. Here, by-pass diodes are connected parallel to a number of solar cells. Under normal operating conditions, the diodes are blocked compared to the voltage generated by the cells. When shading occurs, the reverse of the voltage was observed in that specific section which enables the by-pass diode in parallel to conduct the current. It was observed that; the current of the un-shaded flows through the by-pass diode and the power/voltage characteristics shows a second local maximum. Also, the shaded cell was only loaded with that fraction of power produced by the un-shaded cells of that section.

[1] V. Quaschning and R. Hanitsch,"Numerical simulation of current-voltage characteristics of photovoltaic systems with shaded solar cells," Solar Energy, vol. 56, no. 6, pp. 513–520, 1996.

[2] J. H. R. Enslin, M. S. Wolf, D. B. Snyman, and W. Swiegers, "Integrated photovoltaic maximum power point tracking converter," IEEE Transactions on Industrial Electronics, vol. 44, no. 6, pp. 769–773, 1997.

[3] W. Herrmann, W. Wiesner, and W. Vaassen, "Hot spot investigations on PV modules – new concepts for a test standard and consequences for module design with respect to bypass diodes," in Proceedings of the 26th IEEE Photovoltaic Specialists Conference, pp. 1129–1132, October 1997.

[4] N. D. Kaushika and N. K. Gautam, "Energy yield simulations of interconnected solar PV arrays," IEEE Transactions on Energy Conversion, vol. 18, no. 1, pp. 127–134, 2003.

[5] M. Klenk, S. Keller, L. Weber et al., "Investigation of the hotspot behaviour and formation in crystalline silicon Power cells, PV in Europe, From PV technology to energy solutions," in Proceedings of the International Conference, pp. 272–275, 2002.

[6] A. Woyte, J. Nijs, and R. Belmans, "Partial shadowing of photovoltaic arrays with different system configurations: literature review and field test results," Solar Energy, vol. 74, no. 3, pp. 217–233, 2003.

[7] H. S. Rauschenbach, "Electrical output of shadowed solar arrays," IEEE Transactions on Electron Devices, vol. 18, no. 8, pp. 483–490, 1971.

Abstract: Renewable energy sources like solar and fuel cells are emerging as a promising supplementary power sources due to their merits of cleanness, high efficiency, and high reliability. But the output levels of these are low. An isolated bidirectional full-bridge dc–dc converter can be used for interfacing battery to the system. Because of the presence of leakage inductance of the isolation transformer voltage spikes are produced. An isolated bidirectional converter with a flyback snubber can reduce voltage spike caused by the current difference between the current-fed inductor and leakage inductance of the isolation transformer. In this work an isolated bidirectional full bridge dc-dc converter with and without flyback snubber is simulated using MATLAB SIMULINK Tool and compared the simulation results . Also implemented the hardware of boost mode operation of the same converter with input as 10V and compared it with the simulation results.

Keywords: Clamping capacitor, Flyback snubber, , Isolated bidirectional Dc-Dc converter, Leakage inductance, Voltage spikes

[1.] Tsai-Fu Wu, Senior Member, IEEE, Yung-Chu Chen, Jeng-Gung Yang, and Chia-Ling Kuo, "Isolated Bidirectional Full-Bridge DC–DC Converter With a Flyback Snubber, IEEE Transactions On Power Electronics", Vol. 25, No. 7, July 2010
[2.] K.Wang, C. Y. Lin, L. Zhu, D. Qu, F. C. Lee, and J. S. Lai, "Bi-directional DC to DC converters for fuel cell systems," in Proc. Power Electron. Transp., 1998, pp. 47–51.
[3.] S.Yujin and P.N. Enjeti, "A newsoft switching technique for bi-directional power flow, full- bridge DC-DC converter," in Proc. Ind. Appl.Conf., 2002, vol. 4, pp. 2314–2319.
[4.] O. Garcia, L. A. Flores, J. A. Oliver, J. A. Cobos, and J. De la pena, "Bi-directional DC-DC converter for hybrid vehicles," in Proc.Power Electron. Spec. Conf., 2005
[5.] C. Qiao and K. M. Smedley, "An isolated full bridge boost converter with active soft switching," in Proc. Power Electron. Spec. Conf., 2001, pp. 896–903.
[6.] R. Watson and F. C. Lee, "A soft-switched, full-bridge boost converter employing an active- clamp circuit," in Proc. Power Electron. Spec. Conf., 1996
[7.] K. Wang, F. C. Lee, and J. Lai, "Operation principles of bi-directional full-bridge DC/DC converter with unified soft-switching
[8.] scheme and softstarting capability," in Proc. Appl.Power Electron. Conf., 2000, pp. 111–118.
[9.] F. Krismer and J. W. Kolar, "Accurate small-signal model for the digital control of an automotive bidirectional dual active bridge,"
[10.] IEEE Trans. Power Electron., vol. 24, no.12, pp. 2756–2768, Dec. 2009.

Abstract: In this paper two multilevel inverter topologies, a single phase five level inverter and a seven level inverter which is suitable for interfacing a photovoltaic system to the grid is presented. The multilevel inverter uses a Pulse Width Modulation scheme using two reference signals for five level inverter and three reference signals for seven level inverters. The reference signals are identical to each other with an offset equivalent to the amplitude of the carrier signal. A PI controller is used to keep the current injected into the grid sinusoidal and also to keep the DC link voltage constant under varying atmospheric conditions. The multilevel inverter offers much less total harmonic distortion compared to the conventional H- bridge inverter. This is verified through simulation using MATLAB/SIMULINK.

Keywords: Grid connected, Photovoltaic, Proportional-Integral current control, PWM inverter

[1] K.H. Hussein, 1. Muta ,1. Hoshino ,M. Osakada: "Maximum Photovoltaic Power Tracking: an algorithm for rapidly changing atmospheric conditions‟, IEEE Proc Generation, Transmission, Distribution, Vol.142, No.1, January 1995.
[2] J. Rodriguez, J.-S. Lai, and F. Z. Peng, "Multicarrier PWM strategies for multilevel inverters,"IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 724–738, Aug. 2002.
[3] Trishan Esram, Student Member, IEEE, and Patrick L. Chapman, Senior Member, IEEE.: "Comparison of Photovoltaic Array Maximum Power Point Tracking Techniques‟, IEEE transactions on Energy Conversion, vol. 22, no. 2, June 2007.
[4] S. Jain and V. Agarwal,"Comparison of the performance of maximum power point tracking schemes applied to single-stage grid-connected photovoltaic systems‟, IET Electr. Power Appl., 2007, 1, (5), pp. 753 –762
[5] Jeyraj Selvaraj and Nasrudin A. Rahim,Senior Member, IEEE, "Multilevel Inverter For Grid-Connected PV System Employing Digital PI Controller‟, IEEE transactions on Industrial Electronics, Vol. 56, No. 1, January 2009
[6] Nasrudin A. Rahim,Senior Member, IEEE, Krismadinata Chaniago,Student Member, IEEE, and Jeyraj Selvaraj , "Single-Phase Seven-Level Grid-Connected Inverter for Photovoltaic System‟ , IEEE Transactions on Industrial Electronics, Vol. 58, No. 6, June 2011

Abstract: Recent advances in the development of semiconductors allow the realization of low cost hardware architecture for implementing Barker and Nested binary codes suitable for radar applications. Due to the fast development in Digital Signal Processors (DSP) they are used in radar signal processing. Radar signal processing is defined as exploitation of the received signal represented in digital form to extract the desired information while rejecting unwanted signals. DSP's are used for implementing many of the radar applications. FPGA based implementation of Barker and Nested binary codes are presented and are suitable for real time applications. FPGA provides a reconfigurable solution for implementing DSP applications. Since FPGA's can be reconfigured in hardware, FPGA's offers complete hardware customization for implementing various pulse compression codes. The implementation of Barker and Nested binary codes utilizes the Linear Feedback Shift Registers [LFSR], exhaustive search method. The performance of these codes is given in terms of MeritFactor(MF). The performance measures are calculated offline on a host PC in Matlab for the codes generated by VHDL program. The synthesized binary sequences have good MF values compared with previous work in the literature.

Keywords: Linear Feedback Shift Register(LFSR), Barker codes, Nested binary codes, Linear feedback shift registers, Merit Factor (MF), Auto Correlation function(ACF), Ambiguity Function (AF).

[1] Turin, G. "An introduction to matched filters." Information Theory, IRE Transactions on 6.3 (1960): 311-329.

[2] Oraizi, Homayoon, and A-R. Sharifi. "Design and optimization of broadband asymmetrical multisection Wilkinson power divider." Microwave Theory and Techniques, IEEE Transactions on 54.5 (2006): 2220-2231.

[3] Wang, Yuxi, and Yebing Shen. "Optimized fpga realization of digital matched filter in spread spectrum communication systems." Computer and Information Technology Workshops, 2008. CIT Workshops 2008. IEEE 8th International Conference on. IEEE, 2008.

[4] Balaji, N., K. Subba Rao, and M. Srinivasa Rao. "FPGA implementation of the ternary pulse compression sequences with good discrimination factor values."Computer Engineering and Technology, 2009. ICCET'09. International Conference on. Vol. 2. IEEE, 2009.

[5] R. H. Barker, "Group synchronizing of binary digital systems, in Communication theory", Butterworth, London, 1953, pp. 273-287.

[6] Turyn, R., "On Barker codes of even length", Proceedings of the IEEE, vol. 51, no. 9,September 1963, p. 1256.

[7] Rao, B. V., and A. A. Deshpande. "Why the Barker sequence bit length does not exceed thirteen?." (1988).

[8] Levanon. N, Mozeson, "Radar Signal", Wiley, New York, 2004.

[9] Mark.A.richards, "Fundamentals of radar signal processing, McGraw-hil"l, 2005 [10] NagaJyothi, A., and K. Raja Rajeswari. "Cross-correlation of Barker code and Long binary signals." International Journal of Engineering Science 3.12 (2011): 8348-8356.

Abstract: This paper analyzes the temperature effect on the power generation of building integrated photovoltaic application in Bangladesh. Again this paper shows that how power generation is affected due to variation of azimuth angle. Finally this paper also depicts that how solar irradiation is varied with respect to time duration. From analysis, it is seen that around 10.05% power increment is occurred when tilt/azimuth angle is varied from 21°/180° to 21°/0° at the temperature of 30° taking consideration of Bangladesh climate.

Keywords : Temperature, azimuth angle, solar irradiation.

[1] Mark W. Davis, Brian P. Dougherty & A. Hunter Fanney, Prediction of Building Integrated Photovoltaic Cell Temperatures (Transactions of ASME, the Journal of Solar Energy Engineering, Special issue: Solar Thermo chemical Processing, vol.123, No. 2, PP.200-210, August 2001). http://fire.nist.gov/bfrlpubs/build01/PDF/b01037.pdf
[2] Poh Khai Ng and Nalanie Mithraratne, "A Selection Framework For The Integration Of Semitransparent Bipv Windows In Singapore", Department of Architecture, School of Design and Environment, National University of Singapore, Singapore, http://www.inta2012.org/papers/inta12-46.pdf.
[3] L. Maturi, W. Sparber ,B. Kofler, W. Bresciani," ANALYSIS AND MONITORING RESULTS OF A BIPV SYSTEM IN NORTHERN ITALY", Institute for Renewable Energy, EURAC research, Viale Druso 1, 39100 Bolzano (BZ), Italy, http://www.eurac.edu/en/research/institutes/renewableenergy/Publications2/Documents/EURAC_RenEne_PVSEC2010_Maturi-Sparber-Kofler-Bresciani.pdf .
[4] Joseph Durago, Photovoltaic emulator adaptable to irradiance, temperature and panel-specific I-V curves, California Polytechnic State University, MSEE Thesis, June 2011.
[5] G. S. Campbell and J. M. Norman, "Introduction to Environmental Biophysics. 2nd ed. New York: Springer-Verlag. Pp. 167–183, 1998
[6] Reindl DT, Beckman WA, Duffie JA, "Diffuse fraction correlations", Solar Energy 1990; 45:1-7.
[7] F.J. Batlles et al, "Empirical modeling of hourly direct irradiance by means of hourly global irradiance", Energy 25: 675-688, 2000.
[8] L.T. Wong and W.K. Chow, "Solar radiation model", Applied Energy 69: 191–224, 2001
[9] Z. Abdallah,M. Elhassan,M. Fauzi.Md..Zain, K. Sopian and A. Awadallah, ," Output energy of photovoltaic module directed at optimum slope angle in Kuala Lumpur, Malaysia.", Research Journal of Applied Sciences, Year-2011, Vol. :6, issue: 2, page no.: 104-109, Doi: 10.3923/rjasci.2011.104.109.
[10] F.J. Batlles, M.A. Rubioa, J. Tovarb, F.J. Olmoc and L. Alados-Arboledas, "Empirical modeling of hourly direct irradiance by means of hourly global irradiance", Energy 25: 675-688, 2000.

Abstract: This paper presents modeling and analysis of Wind Energy Conversion Systems (WECS) using MATLAB version R2009a. This paper gives the modeling of the various components wind turbine, generator, controller system, rectifier-inverter, battery, other load equipments including transformer and grid that together form the Wind Energy Conversion system. A test case for the Wind Energy Conversion System has been formed with the aid of the MATLAB version R2009a and also the suggest the ways of improving the stability of the Wind Energy Conversion System (WECS) on interface with the grid.

Keywords: Wind Energy Conversion System (WECS), wind turbine, generator, controller system, rectifierinverter, transformer, grid.

[1] UCTE, Union for coordination of transmission of electricity, Wind Power in the UCTE interconnected System, November 2004.

[2] E. Spooner and A.C. Williamson, Direct coupled permanent magnet generators for wind turbine applications, IEE Proceeding, Electric Power Applications. Vol. 143, N°1, pp.1-8, January, 1996.

[3] M.R.Dubois, H.Polinder and J.A. Ferreira, Comparison of generators topologies for direct –drive wind turbines, ECM 92, Manchester UK, pp. 761-765, 1992.

[4] Thomas Ackerman, Wind Power in Power Systems, Royal Institute of Technology Stockholm, Sweden, Edition: John Wiley and sons, Ltd, 2005.

[5] M.G.Gracia_, M. P. Comech, J.Salla and A. Llombart, Modelling wind farms for grid disturbance studies, Renewable Energy 33 (2008)2109–2121. [6] T.Petru and T.Thirnger, Modelling of wind turbines for power system studies, IEEE Trans. Energy Convers. Vol. 17, N°4, pp. 1132-1139, Nov. 2002.

[7] E.S.Abdin and W.Xu, Control design and dynamic performance analysis of a wind turbine-induction generator unit, IEEE Trans. Energy Convers. Vol. 15, N°1, pp. 91-96, March. 2000.

[8] G.Saccomando, J. Svensson and A.Sannino, Improving voltage disturbance rejection for variable-wind speed wind turbine, IEEE Trans, Energy Convers, Vol. 17, N°3, pp. 422-428, June 2002. [9] http://www.creswindfarm.gr/site1/Articles/ V47_US.pdf

[10] C.M. Ong, Dynamic Simulation of Electric Machinery using Matlab/Simulink, Prentice-Hall PTR, Upper Saddle River, New Jersey, 1998.

Abstract: New VLSI circuit architectures for addition and multiplication modulo (2n - 1) and (2n + 1) are proposed that allow the implementation of highly efficient combinational and pipelined circuits for modular arithmetic. Fast multiplication is very ¬important in DSPs for convolution, Fourier transforms etc. A fast method for multiplication based on ancient Indian Vedic mathematics is proposed in this paper. Among the various methods of multiplications in Vedic mathematics, Urdhva tiryakbhyam is discussed in detail. Urdhva tiryakbhyam is a general multiplication formula applicable to all cases of multiplication. Apart from the Vedic another multiplier with parallel prefix adder architecture is well suited to realize fast end around carry adders used for modulo addition which is known as radix-8 booth multiplier is introduced .a comparative result is analyzed in the implementation.

Keywords: Radix Multiplier, Baugh-Wooley Multiplier, Carry Save array Multiplier.

[1] Y K Yamanaka, T Nishidha, T Saito, M Shimohigashi, and K Shimizu, A. Hitachi Ltd., Tokyo " A 3.8-ns CMOS 16x16-b multiplier using complementary pass-transistor logic," IEEE Journal of Solid-State Circuits, vo1.25, no 2,pp.388-95, 1990.

[2] R Zimmermann and W Fichtner, Fellow, IEEELow-Power" Logic Styles: CMOS Versus Pass-Transistor Logic," IEEE Journal Of Solid-State Circuits, vol. 32, no. 7,pp.1079- 90,1997.

[3] D Markovic, B Nikolic, and V G Oklobdzija, "A general method in synthesis of pass-transistor circuits," Microelectr. J, vol. 31,pp. 991-8,2000.

[4] C H Chang, J Gu, and M Zhang, "A review of O.J8-mm full adder performances for tree structured arithmetic circuits," IEEE Trans. Very Large Scale Integr. (VLSI) Syst. Vol. 13 pp. 686-95, 2005.

[5] Massimo Alioto, Member, IEEE, and Gaetano Palumbo, Senior Member, IEEE, "Analysis and Comparision on Full Adder Block in Submicron Technology," IEEE Transactions On Very Large Scale Integration (VLSI) Systems, vol. 10, no. 6, pp. 806-23, 2002.

[6] L Sousa and R Chaves, "A universal architecture for designing effiCient modulo 2n+ 1 multipliers, " IEEE Trans. Circuits Syst.I: Regular Papers, vol. 52, pp.1166-78, 2005. [7] T Oscal, C Chen, S Wang, and Y W Wu, "Minimization of switching activities of Partial Products for Designing LowPower Multipliers, "IEEE Transaction on Very Large Scale Integration (VLSI) Systems,vol. II, no. 3, pp. 418-433,2008. [8] A. G. Dempster and M. D. Macleod, "Constant integer multiplication using minimum adders," IEE Proc.: Circuits, Devices, Syst., vol. 141, no. 5, pp. 407-413, Oct. 1994.

[9] Y. Voronenko and M. Puschel, "Multiplierless multiple constant multiplication," ACM Transactions on Algorithms, vol. 3, iss. 2, article no. 11, May 2007.

[10] Oscar Gustafsson, "A Difference Based Adder Graph Heuristic for Multiple Constant Multiplication Problems," Int'l Symp. Circuits and Syst., New Orleans, LA, pp. 1097-1100, May 2007.

Abstract: In this Paper, we propose a low-power multiplier design methodology which has multiplier-and-accumulator for high speed and by adopting the new Shift and adds implementation approach. This multiplier is designed by equipping the Power Suppression Technique on DA (distributed arithmetic) algorithm. The Shift and adder will avoid the unwanted addition and thus minimize the switching power dissipation, the performance was improved. When the DA algorithm is directly applied in FPGA (field programmable gate array) to realize FIR (finite impulse response) filter, it is easy to achieve the best configuration in the coefficient of FIR filter, the storage resources and the computing speed. The parallel FIR structures can lead to significant hardware savings for symmetric convolution in odd length from the existing FFA parallel FIR filter, particularly when the length of the filter is large. According to this, the paper provides the detailed analysis and discussion in the algorithm, the memory size and the look up table speed. Also, the corresponding optimization and improvement measures are discussed. The design results of simulation and test show that this method greatly reduces the FPGA hardware resource and the high speed filtering is achieved. The design has a big breakthrough compared to the traditional FPGA realization.

Keywords: DA Algorithm, Fast FIR algorithms (FFAs), parallel FIR, symmetric convolution, very large scale integration (VLSI).

[1] K. K. Parhi, VLSI Digital Signal Processing systems: Design and Implementation. New York: Wiley, 1999.

[2] Z.-J. Mou and P. Duhamel, "Short-length FIR filters and their use in fast nonrecursive filtering," IEEE Trans. Signal Process., vol. 39, no. 6, pp. 1322–1332, Jun. 1991.

[3] J. I. Acha, "Computational structures for fast implementation of L-path and L-block digital filters," IEEE Trans. Circuits Syst., vol. 36, no. 6, pp. 805–812, Jun. 1989.

[4] C. Cheng and K. K. Parhi, "Hardware efficient fast parallel FIR filter structures based on iterated short convolution," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 8, pp. 1492–1500, Aug. 2004.

[5] C. Cheng and K. K. Parhi, "Furthur complexity reduction of parallel FIR filters," in Proc. IEEE ISCAS, May 2005, vol. 2, pp. 1835–1838.

[6] C. Cheng and K. K. Parhi, "Low-cost parallel FIR structures with 2-stage parallelism," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 2, pp. 280–290, Feb. 2007.

[7] I.-S. Lin and S. K. Mitra, "Overlapped block digital filtering," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 43, no. 8, pp. 586–596, Aug. 1996.

[8] Y.-C. Tsao and K. Choi, "Area-efficient parallel FIR digital filter structures for symmetric convolutions based on fast FIR algorithm," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 2, pp. 366–371, Feb. 2010.

[9] D. A. Parker and K. K. Parhi, "Low-area/power parallel FIR digital filter implementations," J. VLSI Signal Process. Syst., vol. 17, no. 1, pp. 75–92, Sep. 1997.

[10] J. G. Chung and K. K. Parhi, "Frequency-spectrum-based low-area lowpower parallel FIR filter design," EURASIP J. Appl. Signal Process., vol. 2002, no. 9, pp. 444–453, Jan. 2002.