iosr-JVSP   Volume-15 ~ Issue-1 ~ Jan. - Feb. 2025

ABSTRACT: Securing online transactions through the implementation of Multi-Factor Authentication (MFA) is a paramount concern in an organization or business enterprise's. The research reviews, understanding, emphasized and applying different MFA types, such as knowledge factors (something you know), possession factors (something you have), and inherence factors (something you are), to fortify online financial security within Abakaliki metropolis of Ebony State- Nigeria.. It also addressed regulatory and compliance considerations related to MFA across various industries, providing a clear view of the subject with the area under study. The research depicts a comprehensive understanding of how to enhance online transaction security using Multi-Factor Authentication within Abakaliki Metropolitan area of Ebonyi State- Nigeria.......

KEYWORDS: Multi-factor, Authentication, Online, Transaction, Ebonyi-State

[1]. Aloul, F. (2012). Two Factor Authentication Using Mobile Phones. 2012 IEEE/ACS International Conference on Computer Systems and Applications (AICCSA).
[2]. Bonneau, J.; Herley, C.; Van Oorschot, P.C.; Stajano, F. Passwords and the Evolution of Imperfect Authentication. Commun. ACM 2015, 58, 78–87. [Google Scholar] [CrossRef]
[3]. Dimitrios C. Tselios, Ilias K. Savvas and M-Tahar Kechadi (2016). International Journal of Monitoring and Surveillance Technologies Research (pp. 42-61).
[4]. Florencio, D., & Herley, C. (2007). A Large-Scale Study of Web Password Habits. Proceedings of the 16th International Conference on World Wide Web.
[5]. Gunson, N.; Marshall, D.; Morton, H.; Jack, M. User Perceptions of Security and Usability of Single-Factor and Two-Factor Authentication in Automated Telephone Banking. Comput. Secur. 2011, 30, 208–220. [Google Scholar] [CrossRef].

ABSTRACT:Electronic circuits are exposed to very high energy radiation in the harsh conditions of outer space. This leads to soft errors such as single-event upsets (SEU), double-event upsets (DEU) and single-event transients (SET). The memory circuits are the most susceptible to these soft errors resulting in severe data loss. This paper proposes the design for an SRAM cell that is radiation hardened by design (RHBD). A comparative study of the standard SRAM cell and the RHBD SRAM cell indicates that the proposed design is resilient to SEUs and DEUs. The proposed design is an improvement on the 8T SRAM cell design and includes a 20T triple interlocked cell......

Key Word: DEU; Radiation Hardening; RHBD; SET; SEU; DEU; SRAM.

[1]. N. Chen, T. Wei, X. Wei and X. Chen, "A Radiation Hardened SRAM in 180-nm RHBD Technology," 2013 IEEE 11th International Conference on Dependable, Autonomic and Secure Computing, 2013, pp. 159-162
[2]. N. K. Z. Lwin, H. Sivaramakrishnan, K. -S. Chong, T. Lin, W. Shu and J. S. Chang, "Single-Event-Transient Resilient Memory for DSP in Space Applications," 2018 IEEE 23rd International Conference on Digital Signal Processing (DSP), 2018, pp. 1-5
[3]. Yuanyuan Han, Tongde Li, Xu Cheng "Radiation Hardened 12T SRAM With Crossbar-Based Peripheral Circuit in 28nm CMOS Technology," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 7, pp. 2962-2975, July 2021
[4]. C. Naga Raghuram, B. Gupta and G. Kaushal, "Double Node Upset Tolerant RHBD15T SRAM Cell Design for Space Applications," in IEEE Transactions on Device and Materials Reliability, vol. 20, no. 1, pp. 181-190, March 2020
[5]. D. Patel and N. Gajjar, "An Investigation of Single Event Upset Hardened SRAM Bit Cells," 2021 International Conference on Advances in Electrical, Computing, Communication and Sustainable Technologies (ICAECT), 2021, pp. 1-4..

ABSTRACT:The Key Objective is HDL RTL Design Architecture of Ultra high multi Clock Frequency Speed Rate ( MHz, GHz, THz, PHz, EHz, ZHz, etc) Bits Per Second Baud Rate ) P.R.B.S(Pseudo Random Binary Sequence) Transceiver Soft A.S.I.C IP Core product for identification of the property of Different Pseudo Random Binary Sequence Patterns (Seed Words) of 2e7-1, 2e10-1, 2e15-1, 2e23-1, 2e31-1 tapped elements as per C.C.I.T.T-I.T.U Standards and IEEE-754 Single and Double Data Rate Data Precision Standards (32 bit & 64 Bit Data Width ) suited for Very Advanced......

Key Word: P.R.B.S- Pseudo Random Binary Sequence, Wi-Fi-Wireless Fidelity, F.P.G.A – Field Programmable Gate Array, IDE – Integrated Development Environment. C.C.I.T.T- Consulting Committee for International Telegraph and Telephone, I.T.U- International Telecommunication Union, A.S.I.C- Application Specific Integrated Circuit, E.D.A- Electronic Design Automation.

[1]. "ITU-T Recommendation O.150". October 1992.
[2]. Tomlinson, Kurt (4 February 2015). "PRBS (Pseudo-Random Binary Sequence)". Bloopist. Retrieved 21 January 2016.
[3]. Paul H. Bardell, William H. McAnney, and Jacob Savir, "Built-In Test for VLSI: Pseudorandom Techniques", John Wiley & Sons, New York, 1987.
[4]. Wikipedia, "http://en.wikipedia.org/wiki/ Pseudorandom_binary_sequence"
[5]. Wikipedia "http://en.wikipedia.org/wiki/ Linear_feedback_shift_register.

ABSTRACT:In this paper, we propose a new paradigm for clock distribution that uses current, rather than voltage, to distribute a global clock signal with reduced power consumption. The Current-mode (CM) signaling can be used for one-to-many clock distribution network. To accomplish this, we create a new high-performance current-mode pulsed flip-flop with enable (CMPFFE) using Tanner tool in 180nm CMOS technology. When the CMPFFE is combined with a CM transmitter.....

Key Word: Current-mode, Voltage-mode, Clock distribution network, flip-flop, low-power.

[1]. H. Zhang, G. Varghese, and J. M. Rabaey, "Low swing on-chip signaling techniques: Effectiveness and robustness," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 8, no. 3, pp. 264–272, Jun. 2000.
[2]. C. Anderson, J. Petrovick, J. Keaty, J. Warnock, et al, "Physical design of a fourth-generation power GHz microprocessor," in Proc. ISSCC, Feb. 2001, pp. 232–233.
[3]. D. Sylvester and C. Hu, "Analytical modeling and characterization of deep-sub micrometer interconnect," Proc. IEEE, vol. 89, no. 5, pp. 634–664, May 2001.
[4]. A. Katoch, H. Veendrick, and E. Seevinck, "High speed current-mode signaling circuits for on-chip interconnects," in Proc. ISCAS, May 2005, pp. 4138–4141.
[5]. F. Yuan, CMOS Current-Mode Circuits for Data Communications. New York: Springer, Apr. 2007..

ABSTRACT:The Serial Peripheral Interface (SPI) and Inter-Integrated Circuit (I2C) protocols are widely used for communication between microcontrollers, sensors, and other digital devices. The correctness and reliability of these protocols are essential for proper system functioning. Therefore, it is necessary to verify these protocols thoroughly to ensure that they are error-free. In this paper, a novel verification environment......

Key Word: Code coverage; functional coverage; SPI; I2C; System Verilog

[1]. Chetan N, and R. Krishna, "Verification of SPI protocol Single Master Multiple Slaves using System verilog and Universal Verification Methodology (UVM)", International Journal of Engineering Research and Applications, Vol. 11, Issue 7, July 2021.
[2]. Ananthula Srinivas, M.Kiran Kumar, and Jugal Kishore Bhandari., Design and Verification of Serial Peripheral Interface", International Journal of Engineering development and Research, Vol. 1, Issue 3, Dec. 2014, pp. 130 -136.
[3]. System Verilog Tutorial: https://www.chipverify.com/systemverilog/systemverilog tutorial[4]. F.Leens, "An Introduction to I2C and SPI Protocols," IEEE Instrumentation & Measurement Magazine, pp. 8-13, February 2009, DOI: 10.1109/MIM.2009.4762946
[5]. M.Sukhanya, and K.Gavaskar, "Functional Verification Environment for I2C Master Controller using System Verilog", 2017 4th International Conference on Signal Processing, Communications and Networking (ICSCN - 2017), March 16 – 18, 2017, Chennai, INDIA, DOI: 10.1109/ICSCN.2017.8085732.