iosr-JVSP   Volume-9 ~ Issue-2 ~ March-April 2019

ABSTRACT: The binary addition is the basic arithmetic operation in digital circuits and it became essential in most of the digital systems including ALU, microprocessors and DSP. Adders are the basic building blocks in digital integrated circuit based designs. Ripple Carry Adder (RCA) gives the most compact design but takes longer computation time. The time critical applications use Carry Look-ahead scheme (CLA) to derive fast results but they lead to increase in area. Carry Select Adder is a compromise between RCA and CLA in term of area and delay. This paper focuses on the FPGA implementation of carry select adder design using Spartan xc3s50pq208-4 based on Multiplexer using Verilog. The delay and power is minimized. The proposed architecture of carry select adder is synthesized in Xilinx ISE14.7and implemented in Xilinx ISE 10.1 on Spartan xc3s50pq208-4.

Keywords: Carry select adder, Multiplexer, Full adder, Verilog, FPGA, Spartan, Power, delay, Xilinx ISE14.7, Xilinx ISE10.1.

[1]. Somashekhar Malipatil, R. Basavaraju and Praveen kumar Nartam. "Low Power & High Speed Carry Select Adder Design Using Verilog", IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 6, Issue 6, Ver. II (Nov. - Dec. 2016), PP 77-81 e-ISSN: 2319 – 4200, p-ISSN No. : 2319 – 4197.

[2]. Bejagam Divya, Alekhya Bonkuri, Madhavi Bandi, Somashekhar Malipatil, "Design and verification of low power and high speed carry select adder using Verilog", International Journal of Creative Research Thoughts (IJCRT), ISSN:2320-2882, Volume.6, Issue 1, Page No pp.1786 - 1790, March 2018.

[3]. B. Ramkumarnd Harish M Kittur, "Low Power and Area Efficient Carry Select Adder" IEEE Transactions on Very Large Scale Integration (VLSI) Systems, VOL. 20, NO. 2, February 2012.

[4]. B. Ramkumar, Kittur, H.M. and Kannan, P. M. (2010) "ASIC Implementation of Modified Faster Carry Save Adder", Eur. J. Sci. Res., Vol.42, No.1, pp.53–58.

[5]. C.S.Manikandababu "An Efficient CSLA Architecture for VLSI Hardware Implementation" IJMIE, ISSN: 2249-0558, Volume 2, Issue 5, 2012, pp.610-622.

ABSTRACT: Miniaturization being the need of the hour, each system needs to have the least possible area utilized. However in the process of doing the same the speed of the system needs to be considered. As for any system addition is the most basic operation, this paper deals with the analyzing and reviewing of different addition algorithms namely, ripple carry, carry select, carry skip, carry save and carry look ahead adders by performing parallel addition of 8 unsigned numbers each of 12 bits using pipelining technique. Either of the adders above can be used depending on the applications as each of them has tradeoffs in terms of area or speed or power.

Keywords: VLSI, Signal Processing, Adders

[1]. R.P.P. Singh, Parveen Kumar, Balwinder Singh, "Performance Analysis of fast Adders using VHDL", 2009 International Conference on Advances in Recent Technologies in Communication and Computing, October 2009,ISBN: 978-0-7695-3845-7,pp. 189 – 193.
[2]. Mariano Aguirre, Monico Linares, "An Alternative Logic Approach to Implement High-Speed Low-Power Full Adder Cells", SBCCI '05, Proceedings of the 18th annual symposium on Integrated circuits and system design,September 4-7 2005, ISBN: 1-59593-174-0, pp. 166 – 171.
[3]. LuJunming, Shu Yan, Lin Zhenghui and Wang, Ling, "A Novel 10-Transisitor Low-Power High-speed Full Adder Cell", 6th International Conference on Solid-State and Integrated Circuit Technology, October 22-25 2001, ISBN: 0-7803-6520-8, Volume 2, pp. 1155 - 1158.
[4]. Ayman A. Fayed and Magdy A. Bayoumi, "A Low Power 10-Transistor Full Adder Cell for Embedded Architectures",The 2001 IEEE International Symposium on Circuits and Systems, May 6-9 2001, ISBN: 0-7803-6685-9, Volume 4, pp.226 – 229.
[5]. Fatemeh Karami H,Ali K. Horestani, "New Structure for Adder with Improved Speed, Area and Power", International Conference on Networked Embedded Systems for Enterprise Applications, December 8-9 2011, ISBN: 978-1-4673-0495-5, pp. 1-6.

ABSTRACT: An array of numbers or symbols whose values are not based on its preceding value is called Random numbers. The number is said to be random if it does not depends on any calculative algorithm or any seed value. This research paper presents a hardware implementation ofa random number generator using VHDL.The Proposed RNG will be a system where strings of unpredictable bits will be present.Field Programmable Gate Arrays (FPGAs) are an increasingly popular choice of platform for the implementation of cryptographic systems. The random numbers generated by our design are verified against the NIST test for statistical correctness.

Keywords: RNG (random number generator), NIST (National institute of standard and technology).

[1]. A. Johnson, R. Chakraborty and D. Mukhopadhyay, "A PUF-Enable Secure Architecture for FPGA-Based IOT Applications", IEEE Transactions on Multi-Scale Computing System, vol. 1, no. 2, pp. 110-122, 2015.
[2]. A. Rukhin, J. Soto, J. Nechvatal, M. Smid and E. Barker, "A Statistical test suite for random and pseudorandom number generator for cryptographic applications", Nat. Inst. Standards Technol. (NIST),Gaitherburg, MD,USA,DTIC Document, Tech. Rep,, 2001.
[3]. N. Tadic, B. Goll and H. Zimmermann, "Laser Diode Current Driver With (1-t/T)-1 Time Dependence in 0.35-μm BiCMOS technology for Quantum Random Number Generators", IEEE Transactions on Circuits And System-II: Express Briefs, vol. 64, no. 5, pp. 510-514, 2017.
[4]. M. Yalcin, J. Suykens and J. Vandewalle, "True random Bit Generation From a Double-Scroll Attractor", IEEE Transactions On Circuits And System_I : Regular Papers, vol. 51, no. 7, 2004.
[5]. B. Sunar, W. Martin and D. Stinson, "A Provably Secure True random Number Generator with Built-In Tolerance to Active Attacks", IEEE Transactions On Computers, vol. 56, no. 1, pp. 109-119, 2007

ABSTRACT: For any data processing unit, addition is the basic operation to be performed by the adder. But the speed is limited due to carry propagation delay of the adder. Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. Area of regular CSLA can be reduced by using CSLA BEC architecture. This paper presents uniform CSLA(UCSLA) with a modification in the first set of RCA with Cin=0,which can be replaced with carry skip adder(CSKPA) so that delay can be reduced much as compared to CSLA BEC. By considering equal number of input bits to each group of CSLA, the area and power can be reduced efficiently. This work estimates the performance of the proposed designs with the regular designs in terms of delay and area. The proposed design is implemented in Xilinx-14.6. The results analysis shows that the proposed uniform CSLA structure is better than the regular CSLA, CSLA BEC.

Keywords: Area, BEC, CSKPA, CSLA, Delay, MUX, Power, RCA, UCSLA.

[1]. J.M. Rabaey, Digital Integrated Circuits- A design Perspective, Upper Saddle River.NJ: PRENTICE-HALL,2001
[2]. A.Tyagi,"A reduced area scheme for carry-select adders", IEEE Transaction on Computer, vol. 42, pp. 1163-1170, 1993.
[3]. Wang, Y. Pai, C.Song, X., "The design of hybrid carry look-ahead/ carry-select adders," Circuits and Systems
II: Analog and Digital Signal Processing, IEEE Transactions on Volume 49, pp.16-24, 2002.
[4]. Bedrij O. J, "Carry-select adder," IRE Transaction on Electronic Comput- ers, pp.340–344, 1962.
[5]. Ram Kumar B, Kittur H. M, and P. M. Kannan, "ASIC implementation of modified faster carry save adder," European Journal of Scientific Re- search, vol. 42, no. 1, pp. 53–58, 2010.

ABSTRACT: This study presents the Influence of White Noise in the Measurement of Acoustic Impedance and Absorption Coefficients of some Industrial Insulating Materials using white noise generator instead of one-third of octave or sine wave and impedance tube with single moveable microphone. The standing wave method is used to measure the acoustic properties (absorption coefficient and acoustic impedance) of sound absorbing materials. A burst of white noise and a signal processing technique was used. The algorithm is based on the equation of simple harmonic motion, however,distance was used as a variable, instead of time. This measurement allows frequency resolutions as low as 5 Hz in a reasonably short amount of time. Although the frequency resolution of 5 Hz and distance of 1cm may not have affected the sampling rate for each time of measurement, but these features of the frequency resolution and distances used does affect the results by the responses of the signals that is produced.

Keywords: Absorption coefficient, Acoustic Impedance, Sound, white noise.

[1]. Lee, J.-c., Hong, Y. S., Nan, R. G., Jang, M. -K., Lee, c. S., Ahn, S. H., and Kang, Y. -J. " Soundproofing effect of nano particle reinforced polymer composites," Journal of Mechanical Science and Technology 22(8), (2009), 1468-1474.
[2]. Jayawardana, T. S. S., Perera, M. Y. A., andWijesena, G. H. D. Analysis and control of noise in a textile factory. International Journal of Scientific and Research Publications, 4(12),(2014), 1-7.
[3]. Farooq, U. FROM SOUND TO NOISE INSULATION: A JOURNEY. International Journal of Engineering Research and General Science,3(1),(2015), 408-413.https://www.researchgate.net/publication/273695003_FROM_SOUND_TO_NOISE_INSULATION_A_JOURNEY
[4]. Binaebi-Soroh, E.andMontalvao, D. Development of a Time-Efficient Approach to Measure theAcoustic Impedance of Industrial Insulating Materials. Open Journal of Applied Sciences, 9,(2019), 55-67.https://doi.org/10.4236/ojapps.2019.92006

[5]. Moretti, E., Merli, F., Cuce, E. and Buratti, C. Thermal and Acoustic Propertiesof Aerogels: Preliminary Investigation of the Influence of Granule Size. Energy Procedia, 111,(2017), 472-480. https://doi.org/10.1016/j.egypro.2017.03.209

ABSTRACT: Fetal heart features are different from those of adult heart in many aspects. This paper presents the detailed survey on different features of fetal heart, which are P-wave, QRS wave and T-wave amplitude and width, segment intervals like PQ interval, RR interval, Heart rate, Heart rate variability, fetal heart axis, these are the standard and most required features. This paper reviews the different techniques used to analyze fetal ECG such as preprocessing, feature extraction, classifying the fetal ECG into normal and abnormal class. Several studies have been published based on these techniques. Out of these few significant studies have been compared in this paper. According to the literature, classification accuracy claimed is in the range of 92 to 99.68%. Although there has been significant variation in the range of accuracy it is at the cost of various other factors such as computational complexity

[1]. Kim M. J. Verdurmen, CarlijnLempersz, Rik Vullings, Christian Schroer, TammoDelhaas, Judith O. E. H. van Laar and S. GuidOei, "Normal ranges for fetal electrocardiogram values for the healthy fetus of 18–24 weeks of gestation: a prospective cohort study ‟, Verdurmen et al. BMC Pregnancy and Childbirth (2016) 16:227.
[2]. Raviranjan Gupta, "Fetal ECG Extraction Methods‟, thesis in National Institute of Technology Rourkela, 2015.
[3]. Cardiovascular Consultants; 2006. Physiology. [Online]. Available: http://www.cardioconsult.com/Physiology/
[4]. Einthoven W. Uber die Form des menschlichen electrocardiograms, Arch Gesamte Physiol.1895; 60:101–123
[5]. Hurst JW, "Naming of the waves in the ECG, with a brief account of their genesis‟. Circulation. Nov; 1998 98(no. 18):1937–1942. [PubMed: 9799216].

ABSTRACT: Any microprocessor is the heart of any general purpose computing systems which is a form of embedded system. The total efficiency of the system is mainly depends upon the efficiency of the main processing elements. In this paper we proposed efficient hardware architecture for 32-bit microprocessor. The proposed architecture is implemented on Digilent ATLYS (Spartan-6) board and the coding is done by VHDL language. For synthesis purpose we use Xilinx ISE 14.5 version. The proposed architecture is optimized with respect to various hardware parameters such as power, frequency etc. which is discussed in the paper briefly. The main reason for these optimizations is simpler architectures of internal components.

Keywords - RISC Architecture, Microprocessor, FPGA implementation, Parallel Processing, Instruction Set etc.

[1]. https://en.wikipedia.org/wiki/MIPS_architecture.
[2]. Cesar O. Campos-Aguillon, Rene Celis-Cordova, Ismo K. Hanninen, Craig S. Lent, Alexi O. Orlov and G. Regory L. Snider, "A Mini MIPS Microprocessor for Adabatic Computing", IEEE International Conference on Rebooting Computing, pp. 1-7, 2016, USA.
[3]. Buse Uataoglu and Berna Ors Yalcin, "Reliability Analysis of MIPS-32 Microprocessor Register File Designed with Different Fault Tolerant Technique", IEEE International Conference on Signal Processing and Communication Application, pp. 1-6, 2016, Turkey.
[4]. Ahmed S Eissa, Mahmoud A Elmohr, Mostafa A Saleh, Khaled E Ahmed and Mohammed M Farag, "SHA-3 Instruction Set Extension for a 32-bit RISC Processor Architecture", 27th IEEE International Conference on Application Specific System, Architecture and Processors, pp. 233-234, 2016, UK.
[5]. Jikku Jeemon, "Pipelined 8-bit RISC Processor Design using verilog HDL on FPGA", IEEE International Conference on Recent Trends in Electronics, Information and Communication Technology, pp. 2023-2027, 2016, India