iosr-JVSP   Volume-12 ~ Issue-5 ~ Sep. - Oct. 2022

ABSTRACT: The floor-plan design is one of the important problem and this problem can be modeled as a combinatorial optimization problem.Today,VLSI technology has taken a fundamental role in developing most of the high-tech electronic circuits. Even though VLSI design is renowned for its smaller size, lower cost, lower power, high reliability and high functionality, the design process takes long time and produces high risk. In this paper, a new expression......

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[3]. X. Hong, G. Huang, Y. Cai, S. Dong, C. K. Cheng and J. Gu ," Corner block list: an effective and efficient topological representation of non slicing floorplan", Proc. ICCAD, pp. 8-12, 2000.
[4]. Y. C. Chang, Y. W. Chang, G. M. Wu and S. W. Wu, "B* trees: a new representation for non slicing floorplans", Proc. DAC, pp. 458-463, 2000.

ABSTRACT: Skin diseases rate has been increasing for past few decades. Psoriasis is chronic inflammatory skin disease which affects more thgan 3% of population. One of the risk factor in skin cancer is unprotected exposer to UV radiation, which causes various skin diseases. For early diagnosis of skin cancer, psoriasis and dermatophytosis and increases chance for cure significantly. Therefore proposed system used for early prevention and detection named a Image analysis system to detects skin diseases. The image analysis technique where user will able to take skin images of different mole type or rashes type. System will process and analyse the images, which provide notification to user you need medical help. This system provides automatic skin diseases prevention and detection.).

Keywords: Enhancement, Segmentation, statistical analysis, Adaboost classifier

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[5]. Omar Abuzaghleh, Buket D. Barkana, Miad Faezipour, "SKIN cure: A Real Time Image Analysis System to Aid in the malignant melanoma Prevention and Early Detection."Member IEEE SSIAI 2014, pp. 85-88..

ABSTRACT: Super-resolution (SR) become the most important task in image processing because of requirement of high quality of images. It becomes popular in technology like computer vision and pattern recognition. In Single Image Super-resolution (SR) uses the sequences of single low resolution (LR) images from high resolution (HR) to improve the quality of image. The SR is an image processing problem which aims to generate a high resolution (HR) image from low resolution input image. The SR is difficult because of the missing information in the given LR image. Thus in SR it....

Keywords: Accuracy, bi-linear SR, Directional group sparsity, PSNR, Super-Resolution

[1]. Xiaoyan Li, Hongjie He, Ruxin Wang, and Dacheng Tao, "Single Image Super resolution via Directional Group Sparsity and Directional Features", IEEE transaction on image processing, Vol. 24, No. 9 Sept 2015.
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[4]. D. Tao, L. Jin, Y. Wang, and X. Li, "Person reidentification by minimum classification error-based KISS metric learning," IEEE Trans. Cybern., vol. 45, no. 2, pp. 242–252, Feb. 2015.
[5]. C. Xu, D. Tao, and C. Xu, "Multi-view intact space learning," IEEE Trans. Pattern Anal. Mach. Intell., Mar. 2015, doi: 10.1109/TPAMI.2015.2417578.

ABSTRACT: In this paper, we propose a new paradigm for clock distribution that uses current, rather than voltage, to distribute a global clock signal with reduced power consumption. The Current-mode (CM) signaling can be used for one-to-many clock distribution network. To accomplish this, we create a new high-performance current-mode pulsed flip-flop with enable (CMPFFE) using Tanner tool in 180nm CMOS technology. When the CMPFFE is combined with a CM transmitter, the first CM clock distribution network exhibits 32% lower average power compared to traditional voltage mode (VM) clocks. CM clocking can play an important role in low-power systems. CM signaling offers many potential advantages such as higher operating speed, low voltage operation, ease of processing and reduced power consumption compared to voltage-mode (VM) techniques.

Index Terms: Current-mode, Voltage-mode, Clock distribution network, flip-flop, low-power

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[4]. A. Katoch, H. Veendrick, and E. Seevinck, "High speed current-mode signaling circuits for on-chip interconnects," in Proc. ISCAS, May 2005, pp. 4138–4141.
[5]. F. Yuan, CMOS Current-Mode Circuits for Data Communications. New York: Springer, Apr. 2007

ABSTRACT: This paper presents design of a Double Gate (DG) heterostructure based tunnelling FET with Subthreshold less than 60 mV/decade. The designed DG-FET has attained the sub-threshold slope (SS) of 51.5 mV/decade and provides on-current of 1.93 nA/μm2 for Si3N4 as tunnel dielectric material. Due to non-similar doping of the regions there is no ambipolarity in the device characteristics which further reduces the off currents by 9.29fA/μm. The on-current in this structure can be enhanced by increasing the height of the source region. Low threshold voltage (Vth) is achieved due to the band to band tunnelling through thin dielectric. At 4nm the threshold voltage (Vth) is 0.301 V and at 1 nm it lower downs to 0.131 V but at the cost of increased subthreshold slope. The designed structure successfully achieves a high Ion/Ioff ratio of 2.07 x 105 for a gate dielectric thickness of 4nm. It has been observed that as thickness of gate dielectric is scaled down to 1nm, the Ion/Ioff ratio degrades to 1.538 x 102 due to sharp increase in Ioff current.

Keywords: Double Gate (DG), Tunnel FET (TFET), Subthreshold Slope (SS), Heterostructure, Threshold Voltage, Ion, Ioff.

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