iosr-JVSP   Volume-13 ~ Issue-2 ~ Mar. - Apr. 2023

ABSTRACT: Irregular heartbeats due to abnormal electrical heart activity are symptom of Cardiovascular disease (CVD), it is a source of stroke, blood clots, heart failure and other heart-related complications. Most of the developed Electrocardiogram (ECG) based automatic cardiac arrhythmia detection systems require the availability of a large data with all arrhythmias for the training process, and cannot be updated without adequate data and cost. Therefore, this paper aims to develop a continual learning method by introducing incrementally new arrhythmias to a deep learning CVD detection system already trained with old ones. However, due to the catastrophic forgetting phenomenon, the pre-trained model loses its pre-acquired knowledge and performs poorly, if it is subject to a new training process.....

Keywords: Electrocardiogram classification; continual learning; catastrophic forgetting; generative model, contrastive learning.

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[5]. C. Ye, M. T. Coimbra, and B. V. Kumar, "Arrhythmia detection and classification using morphological and dynamic features of ECG signals," 2010, pp. 1918–1921.

ABSTRACT: The Serial Peripheral Interface (SPI) and Inter-Integrated Circuit (I2C) protocols are widely used for communication between microcontrollers, sensors, and other digital devices. The correctness and reliability of these protocols are essential for proper system functioning. Therefore, it is necessary to verify these protocols thoroughly to ensure that they are error-free.
In this paper, a novel verification environment is proposed for the verification of SPI and I2C protocols using SystemVerilog. Since, SystemVerilog incorporates Object oriented Programming (OOPs) concept in Verilog programming language, stimulus generation and its application to the DUT are done at higher abstraction level. Further, the proposed approach involves creating verification environments using the Universal Verification Methodology (UVM) framework and verifying the protocols' functionality and performance.

Keywords: Code coverage; functional coverage; SPI; I2C; System Verilog;.

[1]. Chetan N, and R. Krishna, "Verification of SPI protocol Single Master Multiple Slaves using System verilog and Universal Verification Methodology (UVM)", International Journal of Engineering Research and Applications, Vol. 11, Issue 7, July 2021.
[2]. Ananthula Srinivas, M.Kiran Kumar, and Jugal Kishore Bhandari., Design and Verification of Serial Peripheral Interface", International Journal of Engineering development and Research, Vol. 1, Issue 3, Dec. 2014, pp. 130 -136
[3]. System Verilog Tutorial: https://www.chipverify.com/systemverilog/systemverilog tutorial
[4]. F.Leens, "An Introduction to I2C and SPI Protocols," IEEE Instrumentation & Measurement Magazine, pp. 8-13, February 2009, DOI: 10.1109/MIM.2009.4762946
[5]. M.Sukhanya, and K.Gavaskar, "Functional Verification Environment for I2C Master Controller using System Verilog", 2017 4th International Conference on Signal Processing, Communications and Networking (ICSCN - 2017), March 16 – 18, 2017, Chennai, INDIA, DOI: 10.1109/ICSCN.2017.8085732.