iosr-JVSP   Volume-14 ~ Issue-3 ~ May - Jun. 2024

ABSTRACT: The multiplication is one of the most important arithmetic function in Digital signal processing, ALU and various communication systems. The Multiplication method require more hardware resources and more time than other arithmetic and logical circuits such as Addition, Subtraction etc. But the need for fast computation along with low on chip area and the low power dissipation is increased in recent times. In recent years....

Keywords: Vedic Multiplier, 180 nm, Cadence Virtuoso, Transistor count

[1] M. Durga Madhuri, G. Sweta Sree, D. Raghunadh, G. Panduranga Vittal,And Ch.Suryanarayana5. Implementation Of High Speed Vedic Multiplier. International Journal Of Innovative Science And Research Technology, 2, 2017.
[2] Ahsan Rafiq, Shabbir Majeed Chaudhry, Kamran Sadiq Awan And Muhammad Usman. An Efficient Architecture Of Modified Booth Multiplier Using Hybrid Adder. In 2021 International Bhurban Conference On Applied Sciences And Technologies (Ib- Cast), Pages 648–656, 2021.
[3] J. Jayakumar. Design Of Low Power Multiplier Using Cadence Tool. International Journal For Technological Research In Engineering, Volume 3, March-2016.
[4] V. Rajmohan And O. Uma Maheswari. Low Power Modified Wallace Tree Multiplier Using Cadence Tool. World Engineering& Applied Sciences Journal, L 7, 2016.
[5] Er. Harjinder Singh, Er. Mandeep Sing And Er. Gaurav Mittal . Design Of Low Power Vedic Multiplier By Using 180nm Technology. Internatonal Journal Of Innovative Research In Technology, 1:25–31, 2014.

ABSTRACT: Securing online transactions through the implementation of Multi-Factor Authentication (MFA) is a paramount concern in an organization or business enterprise's. The research reviews, understanding, emphasized and applying different MFA types, such as knowledge factors (something you know), possession factors (something you have), and inherence factors (something you are), to fortify online financial security within Abakaliki metropolis of Ebony State- Nigeria.. It also addressed regulatory and compliance considerations related to MFA across various industries, providing a clear view of the subject with the area under study. The research depicts a comprehensive understanding of how to enhance online transaction security using Multi-Factor Authentication within Abakaliki Metropolitan area of Ebonyi State- Nigeria.

Keywords: Multi-factor, Authentication, Online, Transaction, Ebonyi-State

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ABSTRACT: Irregular heartbeats due to abnormal electrical heart activity are symptom of Cardiovascular disease (CVD), it is a source of stroke, blood clots, heart failure and other heart-related complications. Most of the developed Electrocardiogram (ECG) based automatic cardiac arrhythmia detection systems require the availability of a large data with all arrhythmias for the training process, and cannot be updated without adequate data and cost. Therefore, this paper aims to develop a continual learning method by introducing incrementally new arrhythmias.....

Keywords: Electrocardiogram classification; continual learning; catastrophic forgetting; generative model, contrastive learning.

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ABSTRACT: The Serial Peripheral Interface (SPI) and Inter-Integrated Circuit (I2C) protocols are widely used for communication between microcontrollers, sensors, and other digital devices. The correctness and reliability of these protocols are essential for proper system functioning. Therefore, it is necessary to verify these protocols thoroughly to ensure that they are error-free. In this paper, a novel verification environment is proposed for the verification of SPI and I2C protocols using SystemVerilog. Since....

Key Word: Code coverage; functional coverage; SPI; I2C; System Verilog

[1]. Chetan N, and R. Krishna, "Verification of SPI protocol Single Master Multiple Slaves using System verilog and Universal Verification Methodology (UVM)", International Journal of Engineering Research and Applications, Vol. 11, Issue 7, July 2021.
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[5]. M.Sukhanya, and K.Gavaskar, "Functional Verification Environment for I2C Master Controller using System Verilog", 2017 4th International Conference on Signal Processing, Communications and Networking (ICSCN - 2017), March 16 – 18, 2017, Chennai, INDIA, DOI: 10.1109/ICSCN.2017.8085732.

ABSTRACT: The RAW (Restricted Access Window) component of the IoT network is deployed to reduce traffic and channel contention in dense and heterogeneous sensor network environment. It divides sensor nodes into groups and slots, allowing channel access only to one RAW slot at a time. Several algorithms and improved channel utilization optimization models have been proposed to optimize the RAW parameters, to ensure a contention free network or....

KEYWORDS: Resource allocation, station, network, nodes, simulation

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