iosr-JVSP   Volume-3 ~ Issue-3

ABSTRACT:The study was conducted using plantain peel ash and cassava peel ash as an active ingredient. These peels are agricultural waste materials that litter the whole environment. The study used the peels as alternative source to the much needed lye, in soap making. The usage of these peels will reduce the cost of soap making and also reduce waste materials in our environment and these will reduce diseases caused by these waste. The plantain peels and cassava peels were burnt into ashes and the ashes were turned into solution with water and filtered. The filtrate was boiled with palm kernel oil, until good lathering soaps were obtained, sensory evaluation was conducted using 15 home Economic respondents. The data were analyzed using frequency distribution and percentage. The qualities of the soap evaluated were the colour, odour, lathering ability and texture. The findings showed that the ashes were good alternative, ingredient for soap making. Recommendations were made based on the findings: that the use of the raw materials should be encouraged for soap making to save the country's foreign exchange. There is need to create awareness on the use of the ashes. Home economics graduates should exploit the self employment opportunity in the area of local soap production using these ashes for self-reliance.

[1]. Adewuji, G. O. Obi-Egbedo, N. O and Babayemi, J. O., (2008). Evaluation of ten different African wood species for potash
production. International Journal of Physical Sciences 3; 63-68.
[2]. Amyakoha, E. U (ed) (2009). New Entrepreneurship education and Wealth Creation Strategies 2nd edition. Practical tips for
Economic Empowerment and Survival. Nsukka; Great AP Express Publishers ltd.
[3]. Anyakoha, E. U. (2011). Home Economics for Junior Secondary Schools. Onitsha: African-first Publishers Plc., Nigeria.
[4]. AOAC (1984). Official methods of analysis, association of official analytical Chemists, Washington DC , USA.
[5]. Isaac, A. (ed.) (2005). The Macmillan Encyclopedia London: Published by Macmillan London limited.
[6]. Kirk, R.. E and Othmer, D.F. (1994). Encyclopedia of Chemical Technology 3rd edition P. 573-589.
[7]. Okeke, S. U. N. 92009). Home economics for schools and colleges, Onitsha: Africana First publishers plc Nigeria.
[8]. Onyegbado, C.O., Iyagba, T. E and Offor O. J. (2004). Solid soap production using plantain peels ashes as a source of alkali . Journal
of Applied sciences and Environmental management 6; 73-77.
[9]. Onyekwere, C (1996). Cassava peels ash: An alternative source of caustic soda production. Unpublished B. Eng. Thesis. Department
of Chemical Engineering, University of port Harcourt, Nigeria.

ABSTRACT: In this paper, a new low power pulse-triggered Flip-Flop is designed with enhanced latch where the pulse-generation circuit is constructed using one pmos transistor and Data is transferred through two nmos transistors and a inverter, when compared with the conventional pulse-triggered flip-flops, it consumes only 0.373μw of power to activate the circuit and occupies only less area on chip i.e. 5 transistors and two inverters. The simulation results are done based on CMOS 50 nm technology.

Keywords: Flip-Flop, Low power, Pulse-triggered

[1] Yin-Tsung Hwang, Jin-Fa Lin, and Ming-HwaSheu "Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme" in IEEE Transactions on (vlsi) systems, vol. 20, no. 2, february 2012.

[2] A. G. M. Strollo, D. De Caro, E. Napoli, and N. Petra, "A novel highspeed sense-amplifier-based flip-flop,"IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 11, pp. 1266–1274, Nov. 2005.

[3] S. D. Naffziger, G. Colon-Bonet, T. Fischer, R. Riedlinger, T. J.Sullivan, and T. Grutkowski, "The implementation of the Itanium 2microprocessor,"IEEE J. Solid-State Circuits, vol. 37, no. 11, pp.1448–1460, Nov. 2002.

[4] J. Tschanz, S. Narendra, Z. Chen, S. Borkar, M. Sachdev, and V. De,"Comparative delay and energy of single edge-triggered and dual edge triggered pulsed flip-flops for high-performance microprocessors," inProc. ISPLED, 2001, pp. 207–212.

[5] F. Klass, C. Amir, A. Das, K. Aingaran, C. Truong, R. Wang, A. Mehta,R. Heald, and G. Yee, "A new family of semi-dynamic and dynamic flipflops with embedded logic for high-performance processors,"IEEEJ.Solid-State Circuits, vol. 34, no. 5, pp. 712–716, May 1999.

[6] H. Kawaguchi and T. Sakurai, "A reduced clock-swing flip-flop (RCSFF) for 63% power reduction,"IEEE J. Solid-State Circuits, vol.33, no. 5, pp. 807–811, May 1998.

[7] H. Partovi, R. Burd, U. Salim, F. Weber, L. DiGregorio, and D. Draper,"Flow-through latch and edge-triggered flip-flop hybrid elements," in IEEE Tech. Dig. ISSCC, 1996, pp. 138–139.

ABSTRACT: The Fast Fourier Transform (FFT) is a capable algorithm to compute the Discrete Fourier Transform (DFT) and it's inverse. It has a number of applications in the field of signal processing. The usual butterfly FFT design requires needless computations and data storage which lead to unnecessary power consumption. Use of the IEEE-754 standard 32-bit floating-point format also facilitates using the Fast Fourier Transform (FFT) processors. This paper describes two fused floating-point operations and applies them to the implementation of Fast Fourier Transform (FFT) processors using VHDL. The fused operations are a two-term dot product and add-subtract unit. The FFT processors use "butterfly" operations that consist of multiplications, additions, and subtractions of complex valued data. The statistical results of the fused implementations are slightly more accurate.

Keywords: Fast Fourier Transform (FFT), Floating-Point, Radix-2 Butterfly, VHDL.

[1] Earl E. Swartzlander Jr., and Hani H.M. Saleh, "FFT Implementation with Fused Floating-Point Operations," in IEEE Transactions on Computers, 2012.
[2] IEEE Standard for Floating-Point Arithmetic, ANSI/IEEE Standard 754-2008, Aug. 2008.
[3] Sneha N.kherde and Meghana Hasamnis, "Efficient Design and Implementation of FFT," in International Journal of Engineering Science and Technology, 2011.
[4] H.H. Saleh and E.E. Swartzlander, Jr., "A Floating-Point Fused Dot-Product Unit," Proc. IEEE Int'l Conf. Computer Design (ICCD), 2008.
[5] H.H. Saleh, "Fused Floating-Point Arithmetic for DSP," PhD dissertation, Univ. of Texas, 2008.
[6] H. Saleh and E.E. Swartzlander, Jr., "A Floating-Point Fused Add-Subtract Unit," Proc. IEEE Midwest Symp. Circuits and Systems (MWSCAS), pp. 519- 522, 2008.

ABSTRACT: Power-gating has proved to be one of the most effective solutions for reducing stand-by leakage power in nanometer scale CMOS circuits, and different strategies and algorithms for its application have been proposed recently. Unfortunately, power- gating comes with its own set of costs: Performance degradation, area increase, dynamic power increase and routing congestion. A decision to power-gate a design has to be taken, pros and cons of power-gating have to be properly weighted to achieve optimal results. In this paper, "Figures of Merit" (FoMs) for power-gating can be used by designers to better understand the benefits and costs of power-gating, thereby allowing them to achieve optimal results.

Keywords: Figures of Merit, Leakage current, Power-Gating, Sleep transistor size, Turn off/on time.

[1]. F. Fallah, M. Pedram, "Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits," IEICE Trans. on Electronics, Special Section on Low-Power LSI and Low-Power IP, Vol. E88-C, No. 4, pp. 509-519, Apr. 2005.

[2] K. Roy, et al., "Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits," Proceedings of the IEEE, Vol. 91, No. 2, pp. 305-327, Feb. 2003.

[3] H. Jiang, M. Marek-Sadowska, S. R. Nassif, "Benefits and Costs of Power-Gating Technique," ICCD-05, pp. 559-566, Oct. 2005. [4] K. Shi, D. Howard, "Challenges in Sleep Transistor Design and Implementation in Low-Power Designs," DAC-06, pp. 113-116, Jun. 2007.

[5] A. Sathanur, A. Pullini, L. Benini, A. Macii, E. Macii, M. Poncino, "Timing Driven Row-Based Power Gating," ISLPED-07, pp. 104-109, Aug. 2007.

[6] A. Sathanur, A. Calimera, L. Benini, A. Macii, E. Macii, M. Poncino, "Efficient Computation of Discharge Current Upper Bounds for Clustered Sleep Transistor Sizing," DATE-07, pp. 1-6, Apr. 2007.

ABSTRACT: This paper proposes a generic algorithm for k-bit Analog to Digital Conversion. The proposed algorithm is very fast method of conversion of an analog signal into k-bit digital output in a multi-bit parallel fashion. The algorithm employs m stages, each of which is capable of producing bits such that k/m bits are converted at the same time. Thus, this algorithm can be considered a k = n X m conversion method. The algorithm proposed has been tested for a 4-bit current mode ADC implementation. The simulations have been performed in 0.18μm CMOS technology at the supply voltage of 1.8V using P-SPICE.

[1] Veepsa Bhatia, Neeta Pandey, Asok Bhattacharyya, Application Based comparison of different analog to digital Converter architectures", International Journal of Engineering Science and Technology 2(8), 2010,3396-3404.

[2] Nairn, D.G., Salama, C.A.T., Current- Mode Algorithmic Analog to Digital Converters, IEEE Journal of Solid-State Circuits 25, 1990,997-1004.

[3] C. P. Hurrell, C. Lyden, D. Laing, D. Hummerston, and M. Vickery, "An 18 b 12.5 MS/s ADC with 93 dB SNR" ", IEEE Journal of Solid-State Circuits 45, 2010, 2647-2654.

[4] B. A. Wooley, K. Vleugels, Pipelined A/D Conversion, Handout #22, 2002, EE315.

[5] Ken Poulton, R. Ne®, A. Muto, W. Liu, A. Burstein, and M. Heshami, A 4GSample/s 8bADC in 0.35-¹m CMOS", IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 2002,166-167. [6] Robert H. Walden, Analog-to-digital converter survey and Analysis, IEEE Journal on Selected Areas in Communication, 17(4), 1999,539-550

[7] INC, IMS and IDC,A Novel 1GSPS Low Offset Comparator for High Speed AD,NCM '09 Fifth International Joint Conference, 2009, 1251 – 1254

[8] Matsuzawa, ASIC, Trends in high Speed ADC design, ASICON'07, 7th International Conference on Digital Object Identifier, 2007, 245-248.

[9] R. Khoini-Poorfard, L.B. Lim and D.A. Johns, Time-interleaved oversampling A/D converters, IEEE Transaction on Circuits and Systems - II Analog and Digital Signal Processing 44, 1997, 634-645.

[10] M. Choi and A. A. Abidi, A 6-bit 1.3-Gsample/s A/D converter in 0.35 um CMOS, IEEE Journal of Solid-State Circuits 36, 2001,1847-1858.

ABSTRACT: The development of digital integrated circuits is challenged by higher power consumption as low power circuits are most popular now a days as the scaling increase the leakage power in the circuit also increases rapidly hence various high speed ordered multi-threshold voltage CMOS (MTCMOS) circuit techniques are conferred and evaluated during this paper. Novel dual stack technique is proposed that reduces not only the leakage power but also dynamic power. In this paper, a number of critical considerations in the sleep transistor design and implementation includes header or footer switch selection, Reactivation noise suppression made throughout the sleep to active mode transitions is a vital challenge in MTCMOS circuits.

Keywords: MTCMOS, DUAL STACK, SLEEP TRANSISTOR, DYNAMIC POWER, NOISE SUPPRESSION LEAKAGE POWER.

[1] V. Kursun and E. G. Friedman, Multi-Voltage CMOS Circuit Design, John Wiley & Sons Ltd., 2006, ISBN # 0-470-01023-1.
[2] S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamada, "1-V Power Supply High-Speed Digital Circuit Technology," IEEE Journal of Solid-State Circuits, Vol. 30, No. 8, pp. 847-854,August 1995.
[3] J. Kao and A. Chandrakasan, "MTCMOS Sequential Circuits," Proceedings of the European Solid State Circuits Conference, pp. 317 - 320, September 2001.
[4] S. Shigematsu, S. Mutoh, Y. Matsuya, Y. Tanabe, and J. Yamada, "A 1-V High-Speed MTCMOS Circuit Scheme for Power-Down Application Circuits," IEEE Journal of Solid-State Circuits, Vol. 32, No. 6. pp.861-869, June 1997.
[5] Z. Liu and V. Kursun, "New MTCMOS Flip-Flops with Simple Control Circuitry and Low Leakage Data Retention Capability," Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, pp. 1276-1279, December 2007.
[6] J. Kao, A. Chandrakasan, and D. Antoniadis, "Transistor Sizing Issues and Tool for Multi-Threshold CMOS Technology," Proceedings of the IEEE/ACM International Design Automation Conference, pp. 409 - 414, June 1997.
[7] B. H. Calhoun, F. A. Honore, and A. P. Chandrakasan, "A Leakage Reduction Methodology for Distributed MTCMOS," IEEE Journal of Solid-State Circuits, Vol. 39, No. 2, pp. 818 - 826, May 2004.
[8] S. A. Tawfik and V. Kursun, "Low-Power and Compact Sequential Circuits with Independent-Gate Fin FETs," IEEE Transactions on Electron Devices,
Vol. 55, Number 1, pp. 60-70, January 2008.
[9] R. Kumar and G. Hinton, "A Family of 45nm IA Processors," Proceedings of the IEEE International Solid-State Circuits Conference, pp. 58-59, February2009.
[10] Z. Liu and V. Kursun, "High Read Stability and Low Leakage SRAM Cell Based on Data/Bitline Decoupling," Proceedings of the IEEE International Systems on Chip (SOC) Conference, pp. 115-116, September 2006.

ABSTRACT: In this project an FPGA based test bed is realized for injecting faults through clock glitches, to result in setup and hold violations. The UART interface is realized on FPGA to provide PC based controlling for this fault injection. The pre-build serial International Data Encryption (IDEA) algorithm synthesis models will be used as test encryption algorithm. The Xilinx Digital clock manager (DCM) component will be used for generation clocks of different frequencies and phase shifts. The encryption module output with faults introduced and without fault introduced is compared as a function of ratio of used clock frequency and maximum frequency of operation reported by synthesis tool. The modules for clock generation, clock switching, interface adopter to IDEA core and UART interface will be realized and tested in FPGA hardware in integrated form. From PC using HyperTerminal commands will be sent to FPGA firmware. Xilinx simulation and synthesis tools are used to this project. Xilinx Spartan family FPGA board along with serial communication with PC will be used for hardware level testing. Xilinx chipscope tools will be used for verifying the output at various levels in FPGA hardware.

Keywords: Brute force attacks, digital clock manager, invasive techniques, international data encryption algorithm, non invasive techniques.

[1] D. Saha, D. Mukhopadhyay and D. RoyChowdhury, "A Diagonal Fault Attack on the Advanced Encryption Standard", IACR Cryptology ePrint Archive, vol. 2009, p. 581, 2009. [2] J. Balasch, B. Gierlichs and I. Verbauwhede, "An In-depth and Black-box Characterization of the Effects of Clock Glitches on 8-bit MCUs", Proc. Workshop on Fault Diagnosis and Tolerance in Cryptography, 2011.
[3]. http://en.wikipedia.org/wiki/International_Data_Encryption_Algorithm
[4]. http://www.limited-entropy.com/fault-injection-techniques
[5]. http://en.wikipedia.org/wiki/Metastability_in_electronics

ABSTRACT: Bioinformatics is a data rich field which provides unique opportunities to use computational techniques, to understand and to organize information associated with Bio molecules such as DNA, RNA, and Proteins. DNA sequences can be converted into RNA and then proteomic sequences using transcription and translation. First these sequences are to be translated into a "gap sequence" consisting of integer numbers. In this paper, Digital signal processing techniques such as Parametric and Non Parametric methods, filtering techniques, transformation domain methods are applied to gap sequences in order to extract gene features such as identification of protein coding DNA regions, identification of reading frames, and similarity between two genomic and proteomic sequences. Extensive experimental results are presented to demonstrate the performance of the method.

Keywords: Auto-regressive, Genomic-signal-processing, matched filter, Period gram, protein coding region.

[1] Shih-Chieh Su, Chia H. Yeh and C.-C Jay Kuo ,Structural Analysis of Genomic Sequences with Matched Filterin,,2003:17-21

[2] Oppenheim AV, Schafer R. Discrete-Time Signal Processing (3rd Edition)(Prentice-Hall, NY 2009.)

[3] Proakis J G, Manolakis DK, Digital Signal Processing (4th Edition)( Prentice Hall, NY 2006).

[4] Stoica P, Moses RL, Spectral Analysis of Signals, Prentice-Hall, NY 2005.

[5] Akhtar M, Epps J, Ambikairajah E, Signal Processing in Sequence Analysis: Advances in Eukaryotic Gene Prediction, IEEE J Select Topics Sign Proc 2008; 3: 310-21.

[6] Hayes M.H., Statistical digital signal processing and modeling, John Wiley & Sons, Inc., New York, USA, 1996.

[7] Juan V. Lorenzo-Ginori , Digital Signal Processing in the Analysis of Genomic Sequences 2009:28-40 [8] Anastassiou, D,Genomic Signal Processing, IEEE Signal Processing Magazine 18,no. 4 2001):8-20.

[9] E. A. Cheever, D. B. Searls, W. Karunaratne, and G. C. Overton,Using signal processing techniques for DNA sequence comparison, in Bioengineering Conference, 1989, pp. 173–174.

[10] Vaidyanathan, P. P. and Byung-Jun Yoon.,Gene and Exon Prediction Using Allpass-Based Filters., In IEEE International Workshop on Genomic Signal Processing and Statistics, CP2-02. Piscataway, NJ: IEEE Press, 2002

ABSTRACT: The design and development of a digital median filter is presented as part of a soft ip-core for an autonomous mobile robot. The median filter filters the output of the measurement module of a line sensor ipcore for the robot. The bubble-sort network architecture is adopted for the median filter design. The effectiveness of the algorithm is verified by Matlab programming. The algorithm is implemented in hardware on a Xilinx Spartan-3 FPGA device as part of the robot's line-sensor ip-core.

Keywords : Bubble-sort, FPGA, IP-Core, Median filter, System-on-Chip, VHDL

[1] Rajul Maheswari, S.S.S.P.Rao and P.G.Poonacha, "FPGA Implementation of Median Filter", Proceedings of Internationa l
Conference on VLSI Design'97, January 4-7, 1997, pp. 523-524.
[2] V.G.Moshnyaga and K.Hashimoto, "An Efficient Implementation of 1-D Median Filter", Proceedings of the 52-th IEEE Midwest
Symposium on Circuits and Systems (MWS2009), Cancun, Mexico, August 2-5, 2009, pp.451-454.
[3] D. S. Richards, "VLSI Median Filters," IEEE Transactions on Acoustics, Speech, and Signal Processing, vol. 38, pp. 1, Jan 199 0.

ABSTRACT: The advances in VLSI technology have led to complex and larger circuits. As the circuits become complex and large, the amount of time required for the design of such circuits increases. The people in the VLSI industry are looking for faster EDA (Electronic Design Automation) tools so as to reduce the design time. Routing is a phase in the design (physical design) of electronic circuits, wherein pins of a net will be interconnected and this uses Rectilinear Steiner Minimum Trees. Rectilinear Steiner Minimum Tree problem is to find a minimum length tree connecting the given set of points using only horizontal and vertical line segments, with the additional set of points (Steiner points). Steiner points are introduced to reduce the total length of the tree and to connect in rectilinear manner. The problem of finding Rectilinear Steiner Minimum Tree is one of the fundamental problems in the field of electronic design automation. This paper provides a comprehensive analysis of the various Rectilinear Steiner Minimum Tree algorithms proposed till date and shows that there is a need for an algorithm or approach to produce better solution quality (reduced wire length) in less time. Rectilinear Steiner Minimum Tree is widely used in global routing phase of VLSI design and wire length estimation.

Keywords: Global Routing, Rectilinear Steiner Minimum Tree, Rectilinear Minimum spanning Tree, VLSI design

[1] Sherwani, Naveed A. Algorithms for VLSI Physical Design Automation. Kluwer Academic Publishers, 1998.
[2] Hanan, Maurice, On Steiner's problem with rectilinear distance, SIAM Journal on Applied Mathematics 14.2 (1966): 255-265.
[3] Garey, Michael R., and David S. Johnson, The rectilinear Steiner tree problem is NP-complete, SIAM Journal on Applied Mathematics 32.4 (1977): 826-834.
[4] Hwang, Frank K, On Steiner minimal trees with rectilinear distance, SIAM journal on Applied Mathematics 30.1 (1976): 104-114.
[5] Ho, J-M., Gopalakrishnan Vijayan, and C. K. Wong, New algorithms for the rectilinear Steiner tree problem, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on 9.2 (1990): 185-193.
[6] Kahng, Andrew B., and Gabriel Robins, On the performance bounds for a class of rectilinear Steiner tree heuristics in arbitrary dimension, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on 11.11 (1992): 1462-1465.
[7] Hasan, N., G. Vijayan, and C. K. Wong, A neighborhood improvement algorithm for rectilinear Steiner trees, Circuits and Systems, 1990., IEEE International Symposium on. IEEE, 1990.
[8] Kahng, Andrew B., and Gabriel Robins, A new class of iterative Steiner tree heuristics with good performance, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on 11.7 (1992): 893-902.
[9] Ting-Hai, Chao, and Hsu Yu Chin., Rectilinear Steiner tree construction by local and global refinement, Computer-Aided Design, 1990. ICCAD-90. Digest of Technical Papers., 1990 IEEE International Conference on. IEEE, 1990.

ABSTRACT: In the present era of Internet multimedia data especially Images and Videos are the most widely used digital format for data transmission. However due to their large data sizes and constraint of low bandwidth capacity of communication channel it is very difficult to transmit them at optimum speed maintaining the signal quality. Compression therefore, is a vital tool that not only reduces the data size thereby leading to faster data transmission but also protects it to some extent from transmission errors. A large variety of Image and Videos compression techniques are employed each having their own strengths and weaknesses. This paper is an effort to present an overview of image and video compression techniques, their working and comparison.

Keywords: Image Compression, Fidelity Criterion, Entropy, JPEG 2000, Video Compression

[1]. A.E Cawkell, Introduction through -A Quick Comparison of Image Compression Techniques-A Guide to Image Processing and Picture Management, Gower Publishing Limited, 1994.
[2]. C.E. Shannon, A Mathematical Theory of Communication, The Bell System Technical Journal,27, 1948,379–423.
[3]. Harris et. al, The JPEG Algorithm for Image Compression: A Software Implementation and some Test Results, Signals, Systems and Computers, Conference, IEEE,2, 2002, 870-875
[4]. Neelamani et al, JPEG compression history estimation for color images, IEEE Transactions on Image Processing, 15, 2006,1365–78
[5]. Jiang et al, JPEG image compression using quantization table optimization based on perceptual image quality assessment, Asilomar Conference on Signals, Systems and Computers, 2011, 225 – 229
[6]. Ebrahimi et al, Secure JPEG 2000-JPSEC, IEEE International Conf. on Acoustics, Speech, and Signal Processing,4, 2003, 716-19
[7]. Tim Borer, Open Technology Video Compression for Production and Post Production, British Broadcasting Corporations, 2007.
[8]. Rao et al, JPEG 2000: Video/Image Processing and Multimedia Communications, International Symposium on VIPromCom, IEEE, 2002, 1 - 6
[9]. Kalra et al, Video codec comparative analysis between H.264 and DIRAC PRO/VC-2 ,Canadian Conference, IEEE, 2011, 951 -955
[10]. Navakitkanok, Improved rate control for advanced video coding (AVC) standard under low delay constraint, International Conference on Information Technology: Coding and Computing, 2, 2004, 664 – 66.