iosr-JVSP   Volume-3 ~ Issue-5

ABSTRACT:Nowadays Electronic devices are portable which requires low power/low voltage requirement to maximize the battery lifetime. We propose Schmitt Trigger based SRAM bitcell that can operate on low supply voltages. The proposed Schmitt trigger SRAM bitcell resolves the fundamental conflicting design requirement of read versus write operation of conventional 6T bitcell and it gives better read-stability as well as better write ability compared to the other bitcell. This work is executed under the Mentor Graphics EDA tools in 350nm, 250nm CMOS technology. ST-2 cell consumes less power than ST-1 cell.

Keywords: low voltage SRAM, Schmitt Trigger (ST), voltage scaling

[2] A. Bhavnagarwala, X. Tang, and J. Meindl, "The impact of intrinsic device fluctuations on CMOS SRAM cell stability", IEEE J.
Solid-state Circuits, vol. 36, no. 4, Apr. 2001.
[3] S. Mukhopadhyay, H. Mahmoodi, and K.Roy, "Modeling of failure probability and statistical design of SRAM array for yield
enhancement in nanoscaled CMOS", IEEE Trans. Computer-Aided Design. Dec. 2005
[4] N. Yoshinobu, H. Masahi, K. Takayuki, and K. Itoh, "Review and future prospects of low-voltage RAM circuits", IBM J. Res.
Devel, vol. 47, 2003
[5] M. M. Khellah, A. Keshavarzi, D. Somasekhar, T. Karnik, and V. De, "Read and write circuit assist techniques for improving
Vccmin off dense 6T SRAM cell", in proc. Int. Conf. Integr. Circuit Design Technol., June. 2008,pp.
[6] B. Zhai, D. Blaauw, D. Sylvester, and S. Hanson, "A sub-200 mV 6T SRAM in 0.13um CMOS", in proc. Int. Solid state Circuits
conf. Feb. 2007.
[7] L. Chang, D. Fried, J. Hergenrother, J. Sleight, R. Dennard, R.R. Montoye, L. Sekaric, S. McNab, W. Topol, C. Adams, K. Guarini,
and W. Haensch, "Stable SRAM cell design for the 32nm node and beyond" , in Proc.VLSI sym.
[8] N. Verma and A. P.Chandrakasan, "65nm 8T sub-Vt SRAM employing sense-amplifier redundancy", in Proc. Int. Solid State
Circuits Conf Feb. 2007.
[9] V. Ramadurai, R. Joshi, and R. Kanj, "A disturb decoupled column select 8T SRAM cell", in Proc. Custom Integr. Circuits Conf.
Sept 2007.

ABSTRACT:Digital signal processing (DSP) is concerned with the representation of discrete time signals by a sequence of numbers or symbols and the processing of these signals. Digital signal processing and analog signal processing are subfields of signal processing. DSP includes subfields like: audio and speech signal processing, sonar and radar signal processing, sensor array processing, spectral estimation, statistical signal processing, digital image processing, signal processing for communications, control of systems, biomedical signal processing, seismic data processing, etc. in this paper mainly concentrate on array signal processing. Array processing involves combining all sensor outputs in some optimal manner so that the coherent signals emitted by the source are received and all other inputs are maximally discarded. Beam forming algorithms are the foundation for all array processing techniques since this is an effective technique to estimate direction of arrival (DOA). The areas in which beam formers play an important role include radar, sonar, seismology etc. in this paper presents comparative study of beam forming techniques and its implementation on ADSP TS 201 processor

Keywords: signal-to-interference-plus-noise ratio (SINR), direction of arrival (DOA), Minimum Variance Distortion less Response (MVDR),

[1] H.L. Van Trees, "Optimum Array Processing - Part IV of Detection, Estimation and Modulation Theory," John Wiley & Sons Inc.,
New York, 2002.
[2] D. Johnson and D. Dudgeon, "Array Signal Processing Concepts and Techniques," Prentice Hall, Upper Saddle River, NJ, 1993.
[3] Van Veen, D.,Buckley, M., "Beam forming: A versatile approach to spatial filtering", IEEE ASSP Magazine, April 1988.
[4] Hamid Krim, Mats Viberg, "Two decades of array signal processing research", IEEE signal Processing Magazine, July 1996.
[5] www.analog.com/en/embedded.../tigersharc/processors/.../index.html

ABSTRACT: In this paper, IMAGE Compression technique is developed with DWT (discrete wavelet transformation). SPIHT Algorithm is used in the dwt process. hardware architecture of 2d dwt have been implemented as a coprocessor in an embedded system. In this IMAGE Compression technique the 2d_dwt is generated by using cascading of two 1d-dwt. This DWT-based image processing system is developed on Spartan3e (FPGA) by using Xilinx EDK tool.

Keywords: Discrete Wavelet Transform (DWT), FPGA, EDK, Micro Blaze, FSL Introduction

[1]. Z. Fan and R. D. Queiroz. Maximum likelihood estimation of JPEG quantization table in the identification of Bitmap Compression. IEEE, 948-951, 2000.

[2]. Charilaos Christopoulos, Athanassios Skodras, Touradj Ebrahimi,"The JPEG2000 still Image coding system: An overview". IEEE, 1103-1127, November 2000.

[3]. G. K. Wallace, "The JPEG Still Picture Compression Standard", IEEE Trans. Consumer Electronics, Vol. 38, No 1, Feb. 1992

[4]. W. B. Pennebaker and J. L. Mitcell, "JPEG: Still Image Data Compression Stndard", Van Nostrand Reinhold, 1993.

[5]. V. Bhaskaran and K. Konstantinides, "Image and Video Compression Standards:

[6]. ISO/IEC JTC1/SC29/WG1 N505, "Call for contributions for JPEG 2000 (JTC 1.29.14, 15444):Image Coding System," March 1997

[7]. ISO/IEC JTC1/SC29/WG1 N390R, "New work item: JPEG 2000 image coding system," March 1997.

[8]. M. Boliek, C. Christopoulos and E. Majani (editors), "JPEG2000 Part I Final Draft International Standard," (ISO/IEC FDIS15444-1), ISO/IEC JTC1/SC29/

[9]. T. Acharya and A. K. Ray, Image Processing: Principles and Applications. Hoboken, NJ: John Wiley & Sons, 2005

[10]. Alex Fukunaga and Andre Stechert, Evolving Nonlinear Predictive Models for Lossless Image Compression with Genetic Programming,

ABSTRACT: A standard image thumbnail is generated by filtering and sub sampling when the blur and noise of an original image is lost since the standard thumbnails do not distinguish between high quality and low quality originals. In this paper an efficient algorithm with a blur - generating component and a noise generating component preserves the local blur and the noise of the originals. The new thumbnails are more representative of their originals for blurry images .The noise generating component improves the results for noisy images but degrades the results for textured images .The decision to use the noise component of the new thumbnails should base on testing with the particular image mix expected for the application.

Keywords: Standard thumbnails, image quality, noise modelling

[1] A.K.Jain Fundamentals of Digital Image Processing.Englewood cliffs NJ; Prentice-Hall,1989.

[2] A.Munoz,T.Blu,and M.Unser,"Least-squares image resizing using finite differences",IEEE Trans.Image Process,2001.

[3] R.Samadani,S.Lim,and D.Tretter, "Representative image thumbnails for good browsing,"in Proc.IEEE Int.Conf.Image Processing,sep2007,vol.II.

[4] Y.Ke,X.Tang,and F.Jing, " The design of high-level features for photo quality assessment,"in IEEE Computer Society Conf.Computer Visionand Pattern Recognition,2006,vol.1.

[5] A.Wondruff,A.Faulring,R.Roshenholtz,J.Morrison,andP.Prolli, "Using thumbnails to search the web,"in Proc.CHI,Apr.2001.

[6] B.Suh,H.Ling,B.Bederson,and .Jacobs,S.Wink "Automatic thumbnails cropping and its effectiveness," Proc.16th Annu.ACM,Dec.2003.

[7] K.Berkner,E.Schwartz,and C.Marle,L.Karamin "SmartNails:Display-and the image-independent thumbnails," in Proc.SPIE Document Recognition and Retrieval XI,Dec.2003.

[8] S.Avidan and A.Shamir, "Seam carving for content-aware image resizing,"ACM Symp.User In Trans.Graphics,vol.26,2007.

[9] L.Wan,W.Feng,Z.Lin,T.Wong, ndT.Ebriamian Z.Liu, "Perceptual image preview,",oct.2008.

ABSTRACT: Coins are integral part of our day to day life and now it becomes a basic need that coins can be sorted and counted automatically. This paper describes Automated Coin Recognition System for the recognition of Indian Coins with translation and rotation invariance. The paper presents a novel approach that uses the normalized local spatial features of the coin image to derive an abstract image. Decomposition of abstract image in to concentric circles is then used to extract a set of compact and effective features. The proposed method uses a single gallery image per coin for the recognition and show a robust and high recognition performance of 97.43% under variable conditions such as rotation and translation.

Keywords: Image abstraction, Hough transform

[1]. R. Bremananth, B. Balaji, M. Sankari, and A. Chitra, .A new approach to coin recognition using neural pattern analysis,. in Proc. IEEE Annual INDICON, 2005, pp. 366.370.
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[3]. K. Hirata and T. Kato, .Query by visual examplecontent based image retrieval,. in Advances in Database Technology - EDBT '92, Berlin, Germany, 1992, pp. 56.71.
[4]. ISO/IEC JTC1/SC29/WG11/N4063, .MPEG-7 Visual part of eXperimentation Model Version 10.0, Singapore, March 2001.
[5]. M. N¨olle, P. Harald, R. Michael, K. Mayer,I. Holl¨ander, and R. Granec, .Dagobert - a new coin recognition and sorting system,. in Proc. DICTA Digital image computing techniques and applications, 2003, vol. 1, pp. 329.338.
[6]. Cai-ming Chen, Shi-qing Zhang, Yue-fen Chen, "A Coin Recognition System with Rotation Invariance," 2010 International Conference on Machine Vision and Humanmachine Interface, 2010, pp. 755-757.
[7]. Shen, L., Jia, S., Ji, Z. and Chen, W.S., "Statictics of Gabor features for coin reco gnition", IEEE International Workshop on Imaging Systems and Techniques, 2009, pp. 295 - 298.
[8]. Gupta, V., Puri, R., Verma, M., "Prompt Indian Coin Recognition with Rotation Invariance using Image
[9]. Subtraction Technique", International Conference on Devices and Communications (ICDeCom), 2011

ABSTRACT: The paper presents the design and synthesis of 64 bit Reduced Instruction Set Computer (RISC) on Spartan-3E FPGA. A computer using few instructions with simple constructs so they can be executed at much faster rate within the CPU without having to use the memory very often. This type of computer is classified as a reduced instruction set of computer is called RISC. One advantage of RISC is that they can execute their instructions very fast because the instructions are so simple. Another more important advantage is that RISC chips require fewer transistors, makes them cheaper to design and produce. The system on chip (SOC) design of 64 bit RISC processor consist of ALU, Shifter, comparator, RAM Memory, Control Unit, Program counter. Top design approach is used to configure the design. The design is synthesized on Spartan -3E FPGA for 33 instructions. VHDL programming language is used to develop the RISC in Xilinx 14.2 ISE design suit and functional simulated on Modelsim 10.1 b software.

Keywords: Complex Instruction set Computer (CISC), Field Programmable Gate Array (FPGA), and System on chip (SOC), Reduced Instruction Set Computer (RISC)

[1] Brunelli Claudio, Cinelli Federico, Rossi Davide, NurmiJari, "A VHDL model And implementation of a coarse grain reconfigurable coprocessor for a RISC core", 2nd Conference on Ph.D. Research in Microelectronics and Electronics Proceedings, PRIME, 2006, p 229232.

[2] Bighneswar Panda. B. Vijay Bhaskar R. Surya Prakash, "32-Bit Risc Processor For Computer Architecture" International Journal of Engineering Research & Technology (IJERT) Vol. 1 Issue 8, Oct – 2012 page 1-6.

[3] Douglas L Perry "VHDL by examples" chapter-12 Top Level System Design, TMH New Delhi page 289-326

[4] H. Elaarag, "A complete design of a RISC processor for pedagogical purposes," Journal of Computing Sciences in Colleges, vol. 25, Issue 2, pp. 205-213, 2009.

[5] Imran Mohammad, Ramananjaneyulu K "FPGA Implementation of a 64-Bit RISC Processor Using VHDL" International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 Vol. 2, Issue 3, May-Jun 2012, pp.2544-2549

[6] Jiang, Hongtu, "FPGA implementation of controller data path pair in custom Image Processor design", IEEE International Symposium on Circuits and Systems Proceedings,2004, p V141V144.

[7] K. Vlachos, T. Orphanoudakis, Y. Papaeftathiou, N. Nikolaou, D. Pnevmatikatos, G. Konstantoulakis, J.A. Sanchez P., "Design and performance evaluation of a Programmable Packet Processing Engine (PPE) suitable for high speed network Processors units", Microprocessors and Microsystems 31, 2007, p 188–199.

[8] Rohit Sharma, Vivek Kumar Sehgal, Nitin Nitin1, PranavBhasker, IshitaVerma "Design and Implementation of a 64-bit RISC Processor using VHDL"UKSim 2009: 11th International Conference on Computer Modelling and Simulation, 978-0-7695-3593-7/09 $25.00 © 2009 IEEE DOI 10.1109/UKSIM.2009.30 page (568-574)

[9] R. Uma "Design and Performance Analysis of 8-bit RISC Processor using Xilinx Tool" International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 Vol. 2, Issue 2, Mar-Apr 2012, pp.053-058 [10] T. Moreo, P. N. Lorente, F. S. Valles, J. S. Muro, C. F. Andrés, Experiences on developing computer vision hardware algorithms using Xilinx system generators, Elsevier Journal of Microprocessors and Microsystems 29, 2005 pp 411- 419.

ABSTRACT: In this paper, we are going to use a practical approach of uniform down sampling in image space and yet making the sampling adaptive by spatially varying, directional low-pass pre-filtering. The resulting down-sampled pre-filtered image remains a conventional square sample grid, and, thus, it can be compressed, transmitted without any change to current image coding standards and systems. The decoder first decompresses the low-resolution image and then up-converts it to the original resolution in a constrained least squares restoration process, using a 2-D piecewise autoregressive model and the knowledge of directional low-pass pre-filtering. The proposed compression approach of collaborative outperforms JPEG 2000 in PSNR measure at low to medium bit rates and achieves superior visual quality, as well. The superior low bit-rate performance of the Collaborative Adaptive Down-sampling and Upconversion (CADU) approach seems to suggest that over-sampling not only wastes hardware resources and energy, and it could be counterproductive to image quality given a tight bit budget.

Keywords: Autoregressive modeling, compression standards, image restoration, image up conversion, low bit-rate image compression.

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