iosr-JEEE   Volume-10 ~ Issue-2 ~ March-April 2015

Abstract: This paper presents simultaneous tuning of power system stabilizer (PSS) and static var compensator (SVC) based controller to enhance power system stability. The design problem is converted into an optimization problem with a time domain simulation based objective function and particle swarm optimization (PSO) is employed to find optimal parameters of controller. The proposed controller is tested with different disturbance like balance fault, unbalance fault, small disturbance over a weakly connected power system. The nonlinear simulation results show that the proposed control schemes effectiveness and ruggedness over a broad range of different disturbances. Further, the proposed design approach is found to be robust and improves stability efficiently.
Keywords: EHV, LFO, PSS, PSO, SMIB, SVC.

[1] Salma Keskes, Wissem Bahloul and Mohamed Ben Ali Kammoun, "Improvement of Power System Stability by Static Var Compensator and Tuning Employing Genetic Algorithm", International Journal of Modern Nonlinear Theory and Application, Vol. 3, pp-113-123, 2014.
[2] Rajendra prasad Narne and P. C. Panda, "PSS with Multiple FACTS Controllers Coordinated Design and Real-Time Implementation Using Advanced Adaptive PSO", International Science Index International Journal of Electrical, Robotics, Electronics and Communications Engineering, Vol:8 No: 1, pp-144-154, 2014.
[3] Saeid Jalilzadeh, Reza Noroozian, Mahdi Sabouri and Saeid Behzadpoor , "PSS and SVC Controller Design Using Chaos, PSO and SFL Algorithms to Enhancing the Power System Stability", Energy and Power Engineering, Vol. no. 3 ,pp-87-95, 2011.
[4] A.Jalilvand, S. Behzadpoor and M. Hashemi , "Imperialist Competitive Algorithm-Based Design of PSS to Improve the Power System", IEEE, 2010.
[5] R. Grondin, I. Kamwa, G. Trudel and L. Gerin-Lajoie, "Modeling and closed-loop validation of a new PSS concept, the multi-band PSS", IEEE Power Engineering Society, General Meeting, July 2003.

Abstract:The paper presents the converter topology for single to three phase matrix converter for the ac traction drives. The converter analysis is presented with source separation and link approach. The conventional carrier based control is employed for the converter to control the output voltage and frequency. The operational feasibility with the three phase ac traction motor (850 kW) is presented. The performance of the converter with the motor is simulated in the PSIM. The results indicate the feasibility of the matrix converter application to retrofit the existing (AC-DC-AC) to (AC-AC) traction drive system.
Index Terms: Matrix Converters, Sinusoidal Pulse Width Modulation, Traction Motors, Variable Speed Drives.

[1]. SatyaSahityaSekhar Nuka.; Dr. R. SaravanaKumar, "Implementation of Sinusoidal PWM Technique for AC-AC Matrix Converter Using PSIM" 978-1-4244-7926-9/11/$26.00©2011IEEE.
[2]. Ashwin Kumar Sahoo.;Meenakshe,; S. S Dash.; and T. Thyagarajan,"Analysis and simulation of Matrix Converter Using PSIM."The 7th International Conference on Power Electronics -October 22-26, 2007/ EXCO, Daegu, Korea.978-1-4244-1872-5/08 IEEE.
[3]. S. I. Kahn, P. D. Ziogas and M. H. Rashid, "A Novel single to three phase static converter," IEEE Transactions on Industry Applications, 1989, Vol. 25, No.1, pp. 143-152.
[4]. Jianmin Xiao.; Wei Zhang.; Hideki Omori,;KeizoMatsui,"A Novel Operation Strategy for Single-to Three-Phase Matrix Converter" Electrical Machines and systems,2009,ICMES-2009/5382800,page 1-6,Cited by:3
[5]. P. Wheeler, J. Rodriguez, J. Clare, Empringham and A. Weinstein., "Matrix converters: A Technology Review," IEEE Transactions on Industrial Electronics, vol. 49, no. 2, April 2002,pp. 276 - 288.

Abstract: Handwriting recognition is a wayto knowthe letters or words are present in handwritten text. This technique is very important to communication between man and machine and can help in handwritten documentsprocessing automatically. It is a part of the Optical Character Recognition (OCR), thatdeal with machine-print only.The proposed system is a character-based recognition and it is a writer independent system. The recognition responsibility of the proposed system is for 52 character classes [uppercases (A-Z) and the lowercases (a-z)]. The suggested system includes the essential stages needed for most of the pattern recognition systems. These stages are the preprocessing stage, the features extraction stage, the pattern matching and classification stage and the postprocessing stage. The proposed methods employ threeDimensional Discrete Multiwavelet transform Critically Sampledand also three Dimensional Discrete Wavelet transform (3D-DMWTCS, DWT)using multiresolution image decomposition techniques working together with multiple classification methods as a powerful classifier. The classification stage is designed by using a minimum distance classifier depending on Euclidean Distance which has a high speed performance. The system design also includes a modest postprocessing stage that makes a consistency between the recognized characters within the same word in relation to their upper and lower cases. Theoverallclassification accuracy of proposed systemscan be obtained are 95.76 percent with 3D-DMWTCS and 94.05percent with 3D-DWT based on the Rimes database.
Key word: 3D-DMWTCS, 3D-DWT, dpi, HWR, RR, OCR, ED, MDC.

[1]. Alhajj R. and Ashraf E., Sept. ―Multiagents to Separating Handwritten Connected Digits‖ IEEE transactions on systems, man, and cybernetics—part a: systems and humans, Volume 35, Issue 5,2005.
[2]. A.-L. Bianne, C. Kermorvant, and L. Likforman-Sulem, ―Context- Dependent HMM Modeling Using Tree-Based Clustering for the Recognition of Handwritten Words,‖ Proc. SPIE DocumentRecognition and Retrieval, 2010..
[3]. Assabie Y. and Bigun J" Writer-independent offline recognition of handwritten Ethiopic characters", In: Proc. 11th ICFHR, August 19-21, Montreal, 2008.
[4]. Ballesteros J., Travieso C.M., Alonso J.B. and Ferrer M.A, ― Slant estimation of handwritten characters by means of Zernike moments‖, IEE electronics letters vol.41 no.20, 29th September,2005
[5]. Bruce K., 2009 ―Multiwavelets for Quantitative Pattern Matching‖ Proceedings of the 42nd Hawaii International Conference on System Sciences, pp 1- 10.

Abstract:This paper not only describes the closed loop reactive power control design procedure but also deals with the study on the application of the Static VAR Compensator for the control of such power in distribution system. Furthermore, the dynamic behavior of the system is analyzed in this paper the operating circuit model of VAR Compensator and Unified Power flow Controller were simulated. The simulation results agree with the theoretical results. This simulation tests under various transient conditions are analyzed this results obtained may lead to correct design of a robust controller for reactive power applications.
Index Terms: FACTS controllers, FACTS, power electronic equipment, Control, PWM.

[1]. S. Mori, K. Matsuno, T. Hasegawa, S. Ohnishi, M. Takeda, M. Seto, S. Murakami, F. Ishiguro, "Development of a Large Static
VAR Generator Using Self-Commutated Inverters for Improving Power System Stability," IEEE Transactions on Power Systems, Vol.
8, No. 1, February,2013, pp. 371-377.
[2]. M.Hirakawa, H. Somiya, Y. Mino, K. Baba, S. Murakami, Y. Watanabe, "Application of Self-Commutated Inverters to Substation
Reactive Power Control," CIGRE Paper 23-205, Paris Session, 2012.
[3]. C. Schauder, M. Gernhardt, E. Stacey, T. Lemak, L. Gyugyi, T.W. Cease, A. Edris, M. Wilhelm, "TVA STATCOM Project: Design,
Installation, and Commissioning," CIGRE Paper 14-106, Paris General Session, 2013.
[4]. C. Schauder, "STATCOM for Compensation of Large Electric Arc Furnace Installations," Proceedings of the IEEE PES Summer
Power Meeting, Edmonton, Alberta, July 2013, pp. 1109-1112.
[5]. D.J. Hanson, C. Horwill, B.D. Gemmell, D.R. Monkhouse, "A STATCOM- Based Relocatable SVC Project in the UK for National Grid," Proceedings of the IEEE PES Winter Power Meeting, New York, January 2012.

Abstract:This paper proposes a review on the designing of Asynchronous Viterbi Decoder. In order to reduce the power consumption and increase the speed, it is necessary to design Asynchronous Viterbi Decoder. Therefore, the aim is to design Asynchronous Viterbi Decoder by using handshaking protocol. This paper focuses on Bundled data protocol to design Asynchronous Viterbi Decoder. This paper also describes study of various units of Viterbi decoder. Viterbi decoders employed in digital wireless communications are complex and dissipiate large power. Asynchronous Viterbi Decoder have significant role in terms of performance because they saves power through not having to generate or distribute a global clock. Instead, timing between blocks is performed by local handshake signals. Asynchronous Viterbi decoders are used in wide range of applications i.e. in Wireless Communications, Digital Television broadcast, Largest applications in cell phones, Pattern recognition, Speech recognition CD ROMS and Magnetic disks etc. In Mobile station Baseband Modem, Viterbi Decoder consumes more than One-third of chip area and power dissipation of the baseband modem. Power efficiency can be increased if total power dissipation is decreased. Battery operated systems required Low power consumption. Asynchronous designs are inherently data driven and are active only when doing useful work, enabling significant savings in power and operating at the average speed of all components.

Keywords: Asynchronous Viterbi Decoder, Bundled Data Protocol, Convolutional Encoder, Viterbi Decoder

[1] M. Santhi, Dr. G. Lakshminarayanan , Surya Vamshi Varadhan;"FPGA based Asynchronous Pipelined Viterbi Decoder using Two Phase Bundled-Data Protocol"; IEEE 2008 International SoC Design Conference
[2] "A Low-Power CSCD Asynchronous Viterbi Decoder for Wireless Applications"; Mohamed Kawokgy, C. André T. Salama; International Symposium on low power Electronics and Design (ISPELD) ,August 27-29 2007,Portland,Oregon USA
[3] T. kalavati Devi and C Venkatesh "Design of Low Power Viterbi Decoder using Asynchronous Techniques", International Journal of Advances in Engineering & Technology,Vol 4, Issue 1, pp. 561-570, July 2012.
[4] Michal Kováč, Michal Kubíček; " Asynchronous Logical System Simulation in VHDL"; Dept. of Radio Electronics, Brno University of Technology, Purkyňova 118, 612 00 Brno, Czech Republic 2008 IEEE.
[5] Mohamed Kawokgy, C. Andre T. Salama;" Low-Power Asynchronous Viterbi Decoder for Wireless Applications" Edward S. Rogers Sr. Department of Electrical and Computer Engineering University of Toronto, Toronto, Ontario M5S 3G4, Canada
[6] Soodeh Aghli Moghaddam, Siamak Mohammadi, and Parviz Jabedar Maralani ; " Comparison of Dual Rail and an Enhanced Bundled Data Asynchronous Protocols Noise Robustness in the GALS NoC Link Application" Proceedings of the 14th International CSI Computer Conference (CSICC'09)

Abstract:Image fusion is a method of integrating all relevant and complementary information from images of same source or various sources into a single composite image without any degradation. Three major fusion methods have been dealt in the literature of image fusion – pixel level, feature level and decision level. In this paper, a novel pixel level fusion called Iterative block level principal component averaging fusion is proposed by dividing source images into smaller blocks, thus principal components are calculated for relevant block of source images. Analyzing quantitative and qualitative metrics such as average mutual information and mean structural similarity index clearly demonstrate that the proposed algorithm proves superior than other algorithms for the fusion of noise free and noise filtered MR images.

Keywords: Image fusion, PCA, AMI, SOM, SSIM,DTCWT.

[1]. Zhiping Xu, Medical image fusion using multi-level extrema, Inf. Fusion, 19,September (2014) 38–48.
[2]. A. Khare, U.S. Tiwary, W. Pedrycz, M. Jeon, Multilevel adaptive thresholding and shrinkage technique for denoising using Daubechies complex wavelet trans-form, Imaging Sci. J. 58 (6) (2010) 340–358.
[3]. A. Khare, M. Khare, Y.Y. Jeong, H. Kim, M. Jeon, Despeckling of medical ultra-sound images using complex wavelet transform, Signal Process. 90 (2) (2010)428–439.
[4]. R. Vijayarajana,∗, S. MuttanbaAnna University, Chennai, IndiabDepartment of ECE, Anna University, Chennai, India. Journal science direct.
[5]. aFnegn gF,eent ga la/ nPdr oTcaeod Xiau E / nPgrionceeedriian gE 0n0g i(n2e0e1r1in) g0 0105– (020001 1) 1271 – 1276
[6]. XiaoyanLuoSchool [6]OFElectronicsandInformationEngineering, ,ChinabDepartmentofAutomation,TsinghuaUniversity,TsinghuaNationalLaboratoryforInformationScienceandTechnology(TNList),100084Beijing,China
[7]. Saad M. Darwish Department of Information Technology, Institute of Graduate Studies and Research, Alexandria University.

Abstract:To reduce energy consumption in any industry, it is necessary to determine the efficiency of rewound induction motor and compare it with the rated efficiency of that motor. If the efficiency of rewound induction motor is found near to the rated efficiency of that motor, then there is no need for any change. If the efficiency of rewound induction motor is found low as compared to rated efficiency of that motor, then it is better to replace that motor with new one. This paper explains the pay back period of new motors and its losses comparison with rewound motors.

Keywords: Rewound induction motors, Rice mill, efficiency, energy losses, payback period.

[1]. Gilbert A. McCoy and John G. Douglass, "Energy Management for Motor Driven System"
[2]. Todd Litman, "Efficient Electric Motor Systems," The Fairmont Press, Inc., 1995
[3]. Proprietary Method for Energy Conservation in Electric Induction Motors Saves Energy, Saves Money, Available at: www.energyconservationindustries.com
[4]. Alaj.n Streicher Hagler, Bailly & Company, "Energy efficiency in the Sugar and Manufacturing Industries". March 1985
[5]. Penrose H. W., "Financial Impact of Electrical Motor System Reliability Programs", All-Test Division, BJM Corp, 2003.
[6]. John S. H., John D. K., "Comparison of Induction Motor Field Efficiency Evaluation Method", IEEE Transactions on Industrial Applications, Vol. 34, No. 1, Jan/Feb 1998.
[7]. Bureau of Energy Efficiency (BEE), Energy Efficiency in Electrical Utilities: Electric Motors, Available at: http://emtindia. com/BEE-Exam/GuideBooks/book3.pdf

Abstract:Leakage power has become a great challenge now a days. As the size of the device shrink the leakage power increases. So the leakage power is the very serious problem in CMOS chips. As we move towards the submicron technology the device consistency and the threshold voltage become smaller. When decreasing the supply voltage, the threshold voltage and the oxide thickness decreases due to this leakage increases. The main motivation of this work is to reduce the leakage of the SRAM. The circuit of the SRAM is designed by using different leakage reduction technique like sleep transistor technique, force stack technique, sleepy stack technique and simulated in the cadence virtuoso tool using 45nm,90nm,180nm process technology.

Keywords: SRAM, leakage power, submicron, threshold voltage, cadence tool.

[1]. J.Narendra, A.Chandrakasan, "Sub threshold leakage modeling and reduction techniques," IEEE/ACM International Conference Computer Aided Design, pp.141 – 148, Nov. 2002.
[2]. "International Technology Roadmap for Semiconductors," Semiconductor Industry Association, 2005. [Online]. Available: http://public. itrs.net. [3]. Xiaodong Zhang, "High Performance Low Leakage Design Using Power Compiler and Multi-Vt Libraries", Synopsys, SNUG, Europe, 2003, www.synopsys.com, 10/9/2007. [4]. Sung Mo Kang and Yusuf Leblebici, "CMOS Digital Integrated Circuits-Analysis and Design", Tata McGraw Hill, Third Edition, New Delhi, 2003. [5]. Anantha P. Chandrakasan, Samuel Sheng and Robert W.Broadersen, "Low Power CMOS Digital Design", IEEE Journal of Solid State Circuits, vol. 27, no. 4, pp. 472-484, April 1992.
[6]. Kim, N., Austin, T., Baauw, D., Mudge, T., Flautner, K., Hu, J., Irwin, M., Kandemir, M., And Narayanan, V., "Leakage Current: Moore's Law Meets Static Power," IEEE Computer, Vol. 36, Pp. 68–75, December 2003.
[7]. V. De and S. Borkar, "Technology and design challenges for low power and Design, 1999, pp. 163-168.