iosr-JVSP   Volume-7 ~ Issue-3 ~ May-June 2017

ABSTRACT: Low power consumption has become apparent need in the area of VLSI digital signal processing. This gives rise to the need of minimization of silicon area which can be done by folding algorithm. As silicon area decreases power consumption of a circuit decreases. Folding transformation is a technique which reduces silicon chip area by combining various arithmetic operations into one operation by time scheduling technique. It is applied on iterative with appropriate folding set. This paper presents an approach to design fast Fourier transform (FFT) architectures using folding transformation...........

Keywords: Data flow graph, Fast Fourier transform, Folding transformation technique, Parallel-pipelined, Radix-3 algorithm.

[1] J. G. Proakis and D. G. Manolakis, Digital Signal Processing: Principle, Algorithms, and Applications, Third edition, Pearson Education 2004.
[2] A. V. Oppenheim and R. W. Schafer, Digital Signal Processing, PHI Learning Private Limited, 2011.
[3] N.Weste, D.Harris and A.Banerjee, CMOS VLSI Design: A Circuits and Systems Perspective, Third edition, Pearson Education 2009.
[4] L. R. Rabiner and B. Gold, Theory and application of Digital Signal Processing, PHI Learning Private Limited, 2012.
[5] R.Woods, J.Mcallister, G.Lightbody and Ying Yi, FPGA-based implementation of Signal Processing Systems, John Wiley & Sons, 2008.

ABSTRACT: Reversible logic has shown wide applications in emerging technologies such as quantum computing, optical computing, and extremely low power VLSI circuits. Recently, many researchers have focused on the design and synthesis of efficient reversible logic circuits. In this work, as an example of reversible logic sequential circuits, we propose a novel reversible logic design of the Universal Shift Register. Here, we proposed a D-flip-flop whose efficiency is shown in terms of garbage output, constant input and number of reversible gates. Using this D flip-flop, efficient universal shift register is proposed. Universal shift register is a register that has both right and left shifts and parallel load capabilities. The proposed designs were functionally verified through simulations using Verilog Hardware Description Language.

Keywords: Reversible Logic, Reversible Gate, Shift Register

[1]. R. Landauer,"Irreversibility and heat generation in the computing process", IBMJ. Research and Development, pages: 183-191, 1961.
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[4]. C. H. Bennett, "Notes on the history of reversible computation",IBM J. Research and Development, 32(1):16-23, January 1988.
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ABSTRACT: ECG conveys information regarding the electrical function of the heart, by altering the shape of its constituent waves, namely the P, QRS, and T waves. ECG Feature Extraction plays a significant role in diagnosing most of the cardiac diseases. This paper focuses on detection of the P-wave, based on 12 lead standard ECG, which will be applied to the detection of patients prone to diseases. The ECG signal contains noise and that noise is removed using Bandpass filter. After elimination of noise, we detect QRS complex which help in detecting the P-Wave............

Keywords: Electrocardiogram, P wave, Wavelet Transform, Discrete Wavelet Transform

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[5]. Saritha, V. Sukanya, and Y. Narasimha Murthy, "ECG Signal Analysis Using Wavelet Transforms", Bulgarian Journal of Physics, vol. 35, pp. 68-77, 2008.

ABSTRACT: Due to augmenting integration densities, technology scaling and variation in parameters, the performance failures would possibly occur for every application. The memory applications are vulnerable to single event upsets and transient errors which may cause malfunctions. This paper deals with the idea of a totally distinctive fault detection and correction technique using EG-LDPC codes with the applying mainly targeted on reminiscences. The majority logic secret writing is used here, since it will correct associate degree outsize type of errors. Albeit the majority secret writing consumes longer, it will be overcome by the projected technique that detects the errors in less cycle time............

Keywords: Majority logic decoding; error correction codes (ECCs); Euclidean geometry low-density parity check (EG-LDPC); memory.

[1]. R. Naseer and J. Draper, "DEC ECC design to improve memory reliability in sub-100 nm technologies," in Proc. IEEE ICECS, 2008, pp.586–589.
[2]. Shih-Fu Liu, PedroRevingo, and Juan Antonio Meastro"Efficient majority fault detection with difference set codes for memory applications", IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 1, pp. 148– 156, Jan. 2012.
[3]. M.A. Bajuraet al., "Models and algorithmic limits for an ECC- based approach to hardening sub-100-nm SRAMs," IEEE Trans. Nucl. Sci., vol. 54, no. 4, pp. 935– 945, Aug. 2007
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[5]. C. W. Slayman, "Cache and memory error detection, correction, and reduction techniques for terrestrial servers and workstations," IEEE Trans. Device Mater. Reliabil. vol. 5, no. 3, pp. 397–404, Sep. 2005..

ABSTRACT: This paper presents implementation of Arithmetic Logic Unit as it is fundamental building block of various computing circuits. 4 bit ALU is designed using Modified Quasi State Energy Recovery Logic (MQSERL) and CMOS logic. For implementing ALU, circuits which are needed are Multiplexer , Full adder and various basic gates such as Inverter ,XOR, AND and OR are designed using both logic style. Comparative power analysis has been done to validate the Proposed MQSERL logic style which gives less power dissipation compared to conventional logic. The Arithmetic and Logic Unit designed using proposed MQSERL logic is 24.14 % and 33.28% power efficient than CMOS logic............

Keywords: Low power VLSI, Quasi static energy recovery logic, Energy efficienty circuits, adiabatic computing, and Arithmetic logic unit.

[1] W. C. Athas, L. J. Svensson, J. G. Koller, N. Tzartzanis, and E. Y.-C. Chou, "Low-Power Digital Systems Based on Adiabatic- Switching Principles," IEEE Trans. VLSI Systems, 2(4), 398-407, Dec. 1994
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[5] Y. Moon and D. K. Jeong, "An efficient charge recovery logic circuit,"IEEE J. SolidState Circuits, vol. 31, pp. 514–522, Apr. 1996

ABSTRACT: With ever increasing IC complexity and aggressive technology scaling towards cutting edge technologies, the SOC timing closure is becoming a tedious, time consuming and challenging task. Also in advanced technology nodes one has to consider the effect of PVT variation, temperature inversion, noise effect on delay, which is adding more scenarios for STA to cover. In this work, we have proposed an algorithm for simultaneous usage of data path ECO and clock path ECO for efficient timing closure in SOC. The algorithm here tries to fix multiple failing end points through simple clock path optimization, instead of performing data path optimization across multiple paths, thus reducing area and power overhead............

Keywords: Engineering Change Order ECO, Clock rescheduling / Clock push pull, physically aware, Distributed Multi Scenario Analysis

[1] Y.P. Chen, J.W. Fang, Y.W. Chang, "ECO timing optimization using spare cells," in Proceedings of International Conference on Computer-Aided Design, pp. 530-535, 2007.
[2] Jui-Hung Hung, Yu-Cheng Lin, Wei-Kai Cheng, Tsai-Ming Hsieh, "Unified approach for simultaneous functional and timing ECO," in IET Circuits Devices Syst, Vol. 10, Iss. 6, pp. 514–521, 2016.
[3] Pei-Ci Wu, Martin D. F. Wong, IvailoNedelchev, Sarvesh Bhardwaj, VidyamaniParkhe, "On Timing Closure: Buffer Insertion for Hold-Violation Removal," ACM 978-1-4503-2730-5/14/06, 2014.
[4] C. Lin and H. Zhou, "Clock skew scheduling with delay padding for prescribed skew domains," in Design Automation Conference, 2007. ASP-DAC'07, Asia and South Pacific, pages 541–546, IEEE, 2007
[5] Subhendu Roy, Pavlos M. Mattheakis, Laurent Masse-Navette, and David Z. Pan, "Clock Tree Resynthesis for Multi-Corner Multi-Mode Timing Closure,"in IEEE transactions on computer-aided design of integrated circuits and systems, vol. 34, no. 4, April 2015

ABSTRACT: The Advanced Microcontroller Bus Architecture (AMBA) is used as the on-chip bus in system-onchip (SoC) designs. APB is low bandwidth and low performance bus used to affix the peripherals like UART, Keypad, Timer and other segment equipment's to the bus architecture. The aim of this paper is to design and implement AMBA APB (Advanced Microcontroller Bus Architecture - Advanced Peripheral Bus) Bridge with efficient deployment of system resources. Clock is a major concern in designing of any digital sequential system. Clock skew is introduced when the difference is generated between the arrival times of clock signal. One of the approaches to minimize clock skew is ripple counter. The three bit down ripple counter approach used. APB Bridge with clock skew minimization technique is implemented in the paper using Verilog HDL. For the simulation purpose, Vivado Design Suite ISim has been used. For the synthesization purpose and design utilization summary Vivado Integrated Design Environment (IDE).

Keywords: System on Chip (SoC), Verilog, AMBA, APB Bridge

[1] AMBA Specifications 2.0, Copyright ARM Limited 1999.
[2] KiranRawat, KanikaSahni, SujataPandey, "Design of AMBA APB Bridge with Reset Controller for Efficient Power Consumption", 9th IEEE International Conference on Industrial and Information System (ICIIS2014), Indian Institute of Information Technology and Management, Gwalior, 15-17 December 2014.
[3] KiranRawat, KanikaSahni, SujataPandey,Ziauddin Ahmad "A Novel Low Power Design Approach To Exploit The Power Usage Of AMBA APB Bridge "in 1st International Conference on Recent cognizance in wireless communication & image processing – ICRCWIP-2014, Springer Publication, Jaipur , 16-17 Jan 2015.
[4] KiranRawat, KanikaSahni, SujataPandey, "RTL Implementation for AMBA ASB APB Protocol at System on Chip Level "in 2nd International Conference on Signal Processing & Integrated Networks", SPIN 2015, Amity University, Noida, 19-20 Feb 2015

ABSTRACT: Object tracking is one of the most important components in numerous applications of computer vision. Color can provide an efficient visual feature for tracking non-rigid objects in real-time. The color is chosen as tracking feature to make the process scale and rotation invariant. The color of an object can vary over time due to variations in the illumination conditions, the visual angle and the camera parameters. This paper presents the integration of color distributions into particle filtering. The color feature is extracted using our novel 4D color histogram of the image, which is determined using JND color similarity threshold and connectivity of the neighboring pixels...............

Keywords:Frame segmentation, object detection, object tracking, particle filter, 4-d histogram, spatial connectivity

[1] Alper Yilmaz, Omar Javed and Mubarak Shah, "Object Tracking: A Survey," ACM Computing Surveys, Vol. 38, No. 4, Article 13, Publication date: December 2006.
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[5] 6. M. Isard and A. Blake, CONDENSATION: Unifying Low-Level and High-Level Tracking in a Stochastic Framework, ECCV, pp. 893-908, Vol. 1, 1998.

ABSTRACT: With the rapid improvement in data exchange, large memory devices have come out in recent past. The operational controlling for such large memory has became a tedious task due to faster, distributed nature of memory units. In the process of memory accessing it is observed that data written or fetched are often encounter with fault location and faulty data are written or fetched from the addressed locations. In real time applications, this error cannot be tolerated as it leads to variation in the operational condition dependent on the memory data. Hence, It is required to have an optimal controlling fault tolerance in content addressable memory. In this paper, we present an approach of fault tolerance approach by controlling the fault addressing overhead, by introducing a new addressing approach using redundant control modeling of fault address unit. The presented approach achieves the objective of fault controlling over multiple fault location in different dimensions with redundant coding.

Keywords: Fault controlling, content addressable memory, recurrent address location

[1]. International Technology Roadmap for Semiconductors. (2007) [Online].Available: http://www.itrs.net/links/2007itrs/home2007.html
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ABSTRACT: Low Power SRAMs have become a critical component of many VLSI chips. Power can be reduced by using either dynamic or static power reduction techniques. Power gating is one of the most effective static leakage reduction methods. In power gating sleep transistors are used. They disconnect the cell from power supply during sleep mode leading to 91.6% less static power dissipation but they also helps in reducing the dynamic power by reducing the power supply. In this paper the effect of sleep transistor in active mode is implemented and resulting SRAM is found to dissipate 32% less power than conventional SRAM.

Keywords: SRAM (Static Random Access Memory); 6T (six transistors); 8T (Eight transistors); BL (bitline); WL (Word line); WS (Word Select)

[1]. De-Shiuan Chiou, Shih-Hsin Chen, and Shih-Chieh Chang, "Sleep Transistor Sizing for Leakage Power Minimization Considering Charge Balancing", IEEE Transactions On Very Large Scale Integration (VLSI) Systems, Vol. 17, No. 9, September 2009.
[2]. http://www.vlsi-basics.com/2013/10/power gating-power-management-technique.html
[3]. Kaijian Shi and David Howard, "Sleep Transistor Design and Implementation – Simple Concepts yet Challenges To Be Optimum", International Symposium on VLSI Design, 2006
[4]. A.Vinod Kumar and A.Raghu Ram, "Sleep Transistors in Leakage Critical Circuits and Insertion Power Network Synthesis" IJISET - International Journal of Innovative Science, Engineering & Technology, Vol. 2 Issue 6, June 2015.
[5]. Vinay Kumar Madasu, "Leakage Power Reduction by Using Sleep Methods ", IJECS Volume 2 Issue 9 September, 2013 Page No. 2842-2847.