iosr-JVSP   Volume-3 ~ Issue-4

ABSTRACT:Wireless sensor network consists of many tiny disposable low power devices called nodes, which are spatially distributed in order to perform various application global tasks. These nodes form a network by communicating with each other either directly or through other nodes. Sensor networks are fundamentally constrained by the difficulty and energy expense of delivery information from sensor to sink. Power saving is a critical issue in wireless sensor networks since sensor nodes are powered by batteries which cannot generally change or recharged. In this paper we have focused on radio communication which is often considered as the main cause of energy consumption. One of the solutions to this problem would be generally achieved by reducing the size of the transmitted/received data through data compression. A new adaptive compression technique will be considered for lossless data compression which reduces the amount of data that must be passed through the network and to the sink and thus have energy benefits that are multiplicative with the number of hops the data travel through the network. Possible extensions of this paper, use RUN LENGTH CODING to compress decompress the data in WSN.

Keywords: WSN, Data Compression, Huffman Coding, Run Length Coding.

[1] Jason Lester Hill, "System Architecture for Wireless Sensor Networks" University of California, Berkeley Spring 2003.
[2] Chris Townsend, Steven Arms Micro Strain,"Wireless Sensor Networks: Principles and Applications" Inc.
[3] Jennifer Yick, Biswanath Mukherjee, Dipak Ghosal "Wireless sensor network survey" Department of Computer Science, University of California, Davis, CA 95616, United States
[4] Ian F. Akyildiz, Weilian Su, Yogesh Sankarasubramaniam, and Erdal Cayirci "A Survey on Sensor Networks" IEEE Communications Magazine August 2002.
[5] Cesare Alippi, Romolo Camplani, Cristian Galperti Dipartimento di Elettronica e Informazione, Politecnico di Milano, "Lossless Compression Techniques in Wireless Sensor Networks: Monitoring Micro acoustic Emissions" IEEE Robotic and Sensors Envir International Workshop ononments Ottawa, Canada, 12-13 October 2007.
[6] Cauligi S. Raghavendra and Viktor K. Prasanna, Caimu Tang "An Energy Efficient Adaptive Distributed Source Coding Scheme in Wireless Sensor Networks" 2003 IEEE.
[7] Qianyu Ye, Yu Liu, Lin Zhang "An Extended DISCUS Scheme for Distributed Source Coding in Wireless Sensor Networks" Beijing University of Posts and Telecommunications Beijing, China.
[8] Francesco Marcelloni and and Massimo Vecchio "A Simple Algorithm for Data Compression in Wireless Sensor Networks" IEEE COMMUNICATIONS LETTERS, VOL. 12, NO. 6, JUNE 2008.
[9] Ming-Bo Lin, Jang-Feng Lee, and Gene Eu Jan "A Lossless Data Compression and Decompression Algorithm and Its Hardware Architecture" IEEE TRANSACTIONS on very large scale integration (vlsi) systems, vol. 14, no. 9, September 2006.

ABSTRACT: Reconfigurable computing is a computer architecture which is intended to fill the gap between the hardware and the software, achieving potentially much higher performance than software, while maintaining a higher level of flexibility than hardware. Most commonly and widely used high speed computing fabrics deployed in reconfigurable computing are field-programmable gate arrays (FPGAs). This paper illustrates the architecture used in reconfigurable computing and also demonstrates the advantages of using reconfigurable computing design over conventional ASIC or a simple microprocessor for achieving high level of performance for a specific application.

Keywords; ASIC – Application Specific Integrated Circuit, FPGA- Field Programmable Gate Array, GPU- Graphics Processor Unit, LUT- Lookup Table, RC- Reconfigurable Computing

[1] Guo, Z., Najjar, W., Vahid, F., and Visser, K: "A quantative analysis of the speedup factors of FPGAs over processors‟. Proc. Int Symp. On FPGAs (ACM Press, 2004)
[2] Elbirt, A. J. and Paar, C., " an FPGA implementation and performance evaluation of the serpent block cipher", ACM/SIGDA International Symposium on FPGAs, 2000, 176-184
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[6] Goldstein, S.C., Schmit, H., Budju, M., Cadambi, S., Moe, M., and Taylor, R.: " PipeRench: a reconfigurable architecture and compiler‟, Computer, 2000, 33, 940, pp. 70-77
[7] Betz, V. and Rose, J.: "FPGA routing architecture: Segmentation and buffering to optimize speed and density‟, ACM/SIGDA International Symposium on FPGAs, 1999, pp. 59-68
[8] Mei, B., Vernalde, S., Verkest, D., De Man, H., and Lauwereins, R.: "ADRES: An architecture with tightly coupled VLIW processor and coarse-grained reconfigurable matrix‟, Lect. Notes Comput. Sci., 2003, 2778
[9] Compton, K., and Hauck, S.: " Reconfigurable computing: a survey of systems and software‟, ACM Comput. Surv., 2002,34, (2), pp. 171-210
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ABSTRACT: Due to Technology scaling the importance of leakage power has significantly increased in the modern day system-on-chip devices. The runtime leakage component during the active state is almost becoming equal to the standby leakage component. Hence Present day research is more focused on reduction of runtime leakage current .we present a novel runtime leakage reduction for 70nm technology. As an attempt to save the leakage power in the active mode, run-time power gating is explored at various design levels. In the present work we propose a power control method based on Transient Time Slot (TTS) of a logic gate. Using static timing analysis, for each logic gate of the circuit we find its idle period (non-transition period) within the clock period. We switch off the power supply during that period which saves significant amount of run time leakage power. The Logic gates are partitioned according to a heuristic algorithm proposed into clusters so that pair of control transistors is attached to each cluster. Power is supplied only during Transient Time Slot. We simulated ISCAC'85 bench mark circuits and observed that there is significant amount of run time leakage saved. We designed a multiplier using the proposed approach and observed about 85% of runtime leakage savings. Later we simulated c6288 netlist which is a ideal transistor netlist and observed that same amount of runtime leakage power is saved as that of TTS method. There is slight increase in the area and delay which is trade off with the leakage savings

Index Terms: Runtime leakage, Transient Time Slot, Optimization function, Partitioning algorithm

[1] A. Agarwal, S. Mukhopadhyay, A. Raychowdhury, K. Roy, anD C. H. Kim. Leakage Power Analysis and Reduction for Nanoscale Circuits. IEEE Micro, 6(2):68–80, 2006.
[2] T. Raja, V. D. Agrawal, and M. L. Bushnell. Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program. In Proc. of the 16th Int'l. Conf. on VLSI Design, pages 527–532, Jan. 2003.
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[4] S.Bhunia, N. Banerjee, Q. Chen, H. Mahmoodi, and K. Roy. A Novel Synthesis Approach for Active Leakage Power Reduction Using Dynamic Supply Gating. In Proc. Of the ACM/IEEE Design Automation Conf., pages 479–484, June 2005.
[5] D. Duarte, Y. F. Tsai, N. Vijaykrishnan, and M. J. Irwin. Evaluating Run-time Techniques for Leakage Power Reduction. In Proc. of the 7th Asia and South Pacific and 15th Int. Conf. on VLSI Design, pages 31–38, 2002.

ABSTRACT: In recent years, a low power design approach has become more appropriate due to the exponentially increasing power dissipation. This has motivated the designers to explore various design approaches to reduce power dissipation in VLSI circuits. Energy recovery circuits based on the adiabatic logic principle have been proved to be a promising approach among various non-conventional low power design methodologies. The CEPAL (Complementary Energy Path Adiabatic Logic) inverter being an adiabatic logic, has proved its advantage through the minimization of the energy dissipation over static CMOS. Its performance is also compared against the CAL (Clocked Adiabatic Logic) inverter, which is a dynamic type of adiabatic logic. This paper presents the implementation of the 2-bit Sklansky tree adder structure, designed with CEPAL logic, which has been chosen due to its increased fan-out that results in reduced latency and improved speed performance. The analyses are carried out using the EDA tool which is the Electric VLSI Design System using 130 nm technology library. Electric is used to draw schematics and to do integrated circuit layouts LT-Spice Tool is used to simulate the SPICE deck which is produced from generated schematics and layouts.

Keywords- Adiabatic logic, CAL, CEPAL, PG Logic, Sklansky tree adder.

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[4] Athas, W.C., Svensson, L., Koller, J.G. et al.: Low-power digital systems based on adiabatic-switching principles. IEEE Transactions on VLSI System. Vol. 2, Dec. 1994, pp. 398-407.

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[6] Matthew Ziegler, Mircea Stan, "Optimal Logarithmic Adder structures with a fan-out of two for minimizing area delay product," IEEE 2001.

[7] J. Sklansky, "Conditional Sum Addition Logic," IRE Transactions on Electronic computers, vol. EC-9, 1960, pp. 226-231.

[8] S.Knowles, "A Family of Adders", Proceeding of the 15th IEEE Symposium on Computer Arithmetic, June 2001, pp.277-281.

[9] R. Ladner and M. Fischer, "Parallel Prefix Computation," Journal of ACM, vol.27,no.4, October 1980, pp. 831-838.
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ABSTRACT: This work implements gabor filter on ARM9 board.Gabor filters are widely used as band pass filters in image processing for texture analysis,feature extraction ,edge detection etc.They have frequency and orientation representation similar to human visual system.They have the property of self similarity that is every filter can be generated from mother wavelet.ARM9 processors have v4t architecture .It has strong arithametical capability.Since the ARM9 has features like camera interface,AHB,Enhanced DSP instruction,the filter imple mented on ARM9 can be used for realtime image processing.This implementation uses Opencv functions Index Terms—filter bank; extraction; gabor kernel;

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