iosr-JVSP   Volume-3 ~ Issue-6

ABSTRACT: Indeed some works on urban settlement and crime are skeptical that specific places can be considered a category capable of differentiating social groups base on their controversial status in other sub-areas of sociology, the twin concept of study of crime and urban communities remain important. Social inequality that shared perceptions of social deprivation have been instrumental in creating a distinct community based collective psychological reaction. It is this specific psychological reaction which in theory has made shanty dwellers more aggressive than non-shanty dwellers. In this paper, we show how spatial inequality goes about constructing difference based on a collective psychological reaction to social deprivation. To do this, the study used some assumptions on key variable 'crime', income' and 'class'. Using regress and regression micro fit 4.1 statistical package, the study revealed that crime in Port Harcourt is not tied to spatial phenomenon but based on the prevalence of certain social forces which determine the dimension and magnitude of crime. The study recommends the inclusion of urban poor in government housing development plan.

Key woeds: Violent, People, Violent Places', Urban, Change, Criminality, Port Harcourt.

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ABSTRACT: This paper is devoted to the design of Quad core crypto processor for executing both Prime field and binary extension field instructions. The proposed design is specifically optimized for Field programmable gate array (FPGA) platform. Combination of two different field (prime field GF(P) and Binary extension field GF(2m)) instructions execution is analyzed. Quad core will execute four instruction at a same time. The design is implemented in Spartan 3E , virtex4 and virtex5. The performance results between them are compared. The implementation result shows the execution of parallelism using dual field instructions.

Keywords: Binary extension field, Cryptoprocessor, FPGA, Primefield

[1] Johannes Wolkerstorfer, "Dual-Field Arithmetic Unit for GF(p) and GF(2m)"Institute for Applied Information Processing and Communications, Graz University of Technology, Inffeldgasse 16a, 8010 Graz, Austria. This work origin from the European Commission funded project USB CRYPT established under contract IST-2000-25169intheInformationSocietyTechnologies(IST)Program.

[2] Jun-Hong Chen, Ming-Der Shieh, Member, IEEE, and Wen-Ching Lin, "A High-Performance Unified-Field Reconfigurable Cryptographic Processor" IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 18, NO. 8, AUGUST 2010.

[3] Michael Grand, Lilian Bossuet2, Guy Gogniat, Bertrand Le Gal, Jean-Philippe Delahaye and Dominique Dallet, "A Reconfigurable Multi-core Cryptoprocessor for Multi-channel Communication Systems", published in "IPDPS - 25th IEEE International Parallel & Distributed Processing Symposium, Anchorage : United States (2011)"

[4] Santosh Ghosh, Debdeep Mukhopadhyay, and Dipanwita Roychowdhury "Secure Dual-Core Cryptoprocessor for Pairings Over Barreto-Naehrig Curves on FPGA Platform" IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,

[5] P.C. Kocher, "Timing attacks on implementations of diffle-hellman, RSA,DSS and other systems," in Adv. Cryptology-CRYPTO'96,LNCS1109,1996,pp.104-113.

[6] D.Kammler, D.Zhang, P.Schwabe,H. charwaechter, M. Langenberg, D. Auras, G. Ascheid, and R. Mathar, "Designing an ASIP for cryptographic pairings over Barreto-Naehrig Curves," CHES'09, LNCS 5747, pp. 254-271,2009.

[7] J. Fan, F. Vercauteren, and I.Verbauwhede, "Faster Fp-arithematic for Cryptographic pairings on Barreto-Naehrig curves," CHES'09, LNCS 5747, pp.240-253, 2009.

[8] D. N. Amanor, C. Paar, J. Pelzl, V. Bunimov, and M. Schimmler, "Efficient hardware architectures for modular multiplication on FPGAs," in proc.Int. Conf. Field Program. LogicAppl.2005,pp.539-542. [9] V. Bunimov and M. Schmiller, "Area and time efficient modular multiplication of large integers," in Proc. ASAP, 2003,pp.400-409. [10] Huapeng Wu, Member IEEE, "Bit-Parallel Finite Field Multiplier and Squarer Using Polynomial Basis", IEEE TRANSACTIONS ON COMPUTERS, VOL. 51, NO. 7, JULY 2002

ABSTRACT: In this paper a semiconductor type MEMS based Hydrogen sulphide gas sensor is proposed. The development of the sensor is done using micromachining and micro fabrication techniques. The major sensing element proposed is tungsten oxide nano-fibers for better enhancement in sensitivity. The synthesis of the nanofibers can be done using the electro spinning technique. The sensor design can be validated using the Intellisuite software using its various CAD modules. The sensor has various applications such as in oil and gas industry.

Keywords: MEMS, micromachining, tungsten oxide nanofibres.

[1] Pat Quinn, Governor and Damon T. Arnold, M.D,M.P.H.,Director, Illinois Department of Public health. Environmental Health Fact Sheet.
[2] David Riddle, Mathisen Way, Poyal Road, Colnbrook , Slough, Danger and Detection of hydrogen sulphide gas in oil and Gas exploration and production. April/May 2009
[3] Hydrogen Sulfide, Oil and Gas, and People's Health By Lana Skrtic, UC Berkley.
[4] Effects of Electronic Charge Transfer between adsorbate and Solid on Chemisorption and Catalysis P.B. Weisz,Socony- Vaccum laboratories,NewJersy.
[5] Synthesis of tungsten oxide nanowires Zongwen Liu, Yoshio Bando and Chengchun Tang. Advanced material laboratory, NIMS, Namiki 1-1, Tsukuba, Ibaraki 305-0044, Japan.
[6] Electrospinning of Nanofibres Dan Li and Younan Xia Advanced Materials, Vol 16, Issue 14, 2Aug 2004.
[7] Large scale synthesis of tungsten oxide nanofibres by electrospinning Xiaofeng Lu, Xincai Liu, Wanjin Zhang, Ce Wang, Yen Wei Journal of Colloid interface Science 298(2006)996-999
[8] H2S sensing properties of noble metal doped WO3 thin film sensor fabricated by micromachining Wei-Han Tao, Ching-Hsiang Tsai Sensors and actuators B 81 (2002) 237-247

ABSTRACT: There are many techniques of image enhancement as well as optimizing the same process in the image processing such as Powell's method, Fast Ostu's method, Histogram equalization (HE) method, Particle swarm optimization (PSO) and Honey bee (HB) algorithm. In this paper, a new approach to automatic image enhancement using honey bee mating optimization is implemented by specifying intensity of the edges pixels and also earlier reported PSO results were used. Further results of previous work i-e PSO and HBMO are compared through different parameters. The obtained results indicate that the proposed Honey bee algorithm yields better results in the terms of both the maximization of number of the pixels in the edges and peak signal to noise ratio (PSNR). Computational time is also relatively small in the Honey bee enhanced image as compared to the PSO case which is earlier reported.

Keyword: Swarm optimization, honey bee mating optimization and image enhancement.

[1] J. Kennedy, R.C. Eberhart, and Y.Shi, Swarm Intelligence, Morgan Kanufmann Publishers, San Francisco, 2001.

[2] J. Kennedy and R. C. Eberhart, "Particle swarm optimization", Proc. of IEEE International conference on Neural Networks (Perth, Australia), vol. 5, no. 3, pp. 1942-1948, 1995.

[3] Braik,M., "Image enhancement using particle swarm optimization", Proc. of the world Congress on Engineering, Vol. 1, July 2007.

ABSTRACT: With the progress of VLSI technology, the number of cores on a chip multiprocessor keeps increasing, Now a days we are increasing the processing level of the chip ,NOC is a best method to interconnect the core with each other core on the chip, In this paper we are creating a network concept on a chip by interconnecting the core with each other core. Then we are reducing the overall chip power and Traffic level by sharing the work load with other cores on the chip, And Dynamic Voltage Frequency Scaling (DVFS) is the technique for monitoring the Frequency/Voltage level of each core on the chip and providing sufficient power to the cores, Application Traffic Prediction Table(ATPT) is a Table that having (low and high) Frequency level table of the Each core. ATPT has very high prediction accuracy. Depends upon the ATPT table voltage/frequency is given to the cores by DVFS.

Keyword: Network On Chip, Traffic prediction, Dynamic voltage frequency scaling, Application traffic prediction table Table

[1]. S. Bell, B. Edwards, J. Amann, R. Conlin, K. Joyce, V. Leung,J. MacKay, and M. Reif. TILE64 Processor: A 64-Core SoC withMesh Interconnect. In IEEE International Solid-State CircuitsConference, February 2008.
[2]. U. Nawathe, M. Hassan, K. Yen, L. Warriner, B. Upputuri, D. Greenhill,A. Kumar, and H. Park. An 8-Core 64-Thread 64b Power-EfficientSPARC SoC. In IEEE International Solid-State Circuits Conference,
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[4]. S. Bell, B. Edwards, J. Amann, R. Conlin, K. Joyce, V. Leung,J. MacKay, M. Reif, L. Bao, J. Brown, M. Mattina, C.-C. Miao,C. Ramey, D. Wentzlaff, W. Anderson, E. Berger, N. Fairbanks,D. Khan, F. Montenegro, J. Stickney, and J. Zook. Tile64 -processor: A 64-core soc with mesh interconnect. In Solid-StateCircuits Conference, 2008.ISSCC 2008. Digest of TechnicalPapers. IEEE International, pages 88–598, Feb. 2008.
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ABSTRACT: This project introduces a tensor perceptual color framework (TPCF) for facial expression recognition (FER), which is based on information contained in color facial images. The TPCF enables multilinear image analysis in different color spaces, and demonstrates that color components provide additional information for robust FER. Using this framework, the components (in either RGB, YCbCr, CIELab space) of color images are unfolded to 2-D tensors based on multilinear algebra and tensor concepts, from which the features are extracted by Log-Gabor filters

[1]. S.M. Lajevardi, "Automatic facial expression recognition: Feature extraction and selection," Signal, Image Video Process., vol. 6, no. 1, pp. 159–169, 2012. [2] "S. Moore and R. Bowden, "Local binary patterns for multi-view facial expression recognition" Compo Vis. Image Understand., vol. 115, no. 4, pp. 541–558, 2011. [3] G. Zhao, X. Huang, M. Taini, S. Z. Li, and M. Pietikäinen, "Facial expression recognition from near-infrared videos," Image Vis. Comput., vol. 29, no. 9, pp. 607–619, Aug. 2011. [4] R. O. Duda, "Pattern Classification", 2nd Ed. New York: Wiley, 2001. [5] A. Mehrabian," Nonverbal Communication". London, U.K.: Aldine, 2007.

ABSTRACT: The complexity of ASIC design has increased at an enormous rate in the last few years. This gives rise to difficulties in verification as well. Assertion Based Verification (ABV) provides a solution to this problem. Assertions are used to capture specifications and design intent in an executable form. They help in detecting the bugs faster and closer to the source. In addition to this ABV has a number of advantages such as, detection of corner cases, help in documentation and provide improved design reuse. With the introduction of many standard languages to capture assertions the ABV methodology has gained a lot of popularity. In addition to this many of the simulation tools available today also provide assertion coverage. In this project Avalon Interrupt Interface was designed and verified using assertions. The project carried out involved six stages: RTL design, linting, behavioral simulation, synthesis, Gate Level Simulation (GLS) and adding of assertions. In this project, an RTL design for Avalon Interrupt Interface was developed in VHDL. Testbench was written in Verliog. The design is verified using Accellera PSL assertions along with the test bench. The results were simulated using Aldec Riviera-PRO 2011.02 simulation tool.

[1] Ben Cohen, Srinivasan Venkataramanan and Ajeetha Kumari, "Using PSL/Sugar for formal and dynamic verification: Guide to Property Specification Language for Assertion-Based Verification", VhdlCohen publishing, 2nd Edition, pp. 1-187, 2004
[2] Assertion-Based Verification, 2003. Available: http://www.synopsys.com/Tools/Verification/Documents/assertion_based_wp.pdf
[3] Property Specification Language Reference Manual, (June 9, 2004), Version 1.1. Available: http://www.eda.org/vfv/docs/PSL-v1.1.pdf
[4] Avalon Interface Specifications, (Aug 2010), Available: http://www.altera.com/literature/manual/mnl_avalon_spec.pdf
[5] SOPC Builder User Guide, Available: http://www.altera.com/literature/ug/ug_sopc_builder.pdf
[6] Aldec ALINT, Available : http://www.aldec.com/products/alint

ABSTRACT: For the most recent CMOS feature sizes (e.g., 180nm), leakage power dissipation has become an overriding concern for VLSI circuit designers. As technology scales into the nano meter regime leakage power and noise immunity are becoming important metric of comparable importance to active power, delay and area for the analysis and design of complex arithmetic and logic circuits. In this project, low leakage 1-bit full adder cells are proposed for mobile applications. Noise immunity has been carefully considered since the significant threshold current of the low threshold voltage transition becomes more susceptible to noise. Since, Adders are heart of computational circuits and many complex arithmetic circuits are based on the addition. The vast use of this operation in arithmetic functions attracts a lot of researcher's attention to adder for mobile applications. In recent years, several variants of different logic styles have been proposed to implement 1-bit adder cells. Therefore a new transistor resizing approach for 1-bit full adder cells to determine the optimal sleep transistor size which reduce the leakage power has been proposed. The simulation results depicts that the proposed design also leads to efficient 1-bit full adder cells in terms of standby leakage power. In order to verify the leakage power, various designs of full adder circuits are simulated using DSCH, Micro wind and Virtuoso (Cadence).

[1] Radu Zlatanovici, Sean Kao, Borivoje Nikolic, "Energy-Delay of Optimization 64-Bit Carry- Lookahead Adders With a 240ps 90nm CMOS Design Example," IEEE J. Solid State circuits, vol.44, no. 2, pp. 569-583, Feb. 2009.
[2] K.Navi, O. Kavehei, M. Rouholamini, A. Sahafi, S. Mehrabi, N. Dadkhai, "Low-Power and High-Performance 1-bit CMOS Full Adder Cell," Journal of Computers, Academy Press, vol. 3, no. 2, Feb. 2008.
[3] Rabaey J. M., A. Chandrakasan, B. Nikolic, Digital Integrated Circuits, A Design Perspective, 2nd Prentice Hall, Englewood Cliffs, NJ, 2002
[4] Pren R. Zimmermann, W. Fichtner, "Low-power logic styles: CMOS versus pass-transistor logic," IEEE J. Solid- State Circuits, vol. 32, pp. 1079–1090, July 1997.
[5] S.G.Narendra and A. Chandrakasan, Leakage in Nanometer CMO Technologies. New York: Springer-verlag, 2006.
[6] K.Bernstein et al., "Design and CAD challenges in sub-90nm CMOS technologies," in Proc. int. conf. comput. Aided Des., 2003, pp.129-136.
[7] "International Technology Roadmap for Semiconductors," Semiconductor Industry Association, 2005. [Online]. Available:http://public.itrs.net
[8] H.Felder and J.Ganger,"Full Chip Analysis of Leakage Power Under Process variations, Including Spatial Correlations, "in proc. DAC, pp.523-528, June2005
[9] Jun Cheol Park and Vincent J. Mooney" Sleepy Stack Leakage Reduction" IEEE transactions on very large scale integration (vlsi) systems, vol.14, no.1. november 2006.

ABSTRACT: Interest in current-mode (CM) filters has been growing due to the fact that current-mode devices have wider dynamic range, improved linearity, and extended bandwidth compared with voltage-mode devices. The commonly used circuit techniques for designing current-mode filters are mainly classified into two categories. One technique is based on the transformation of the voltage-mode circuits to current-mode ones, such as the adjoint network, the RC:CR dual transformation and the inverse-complementary network, etc. The other technique uses the direct current-mode integrators as the basic cell of the design biquad and higher-order filters. Depending on the technology chosen, the frequency range of transconductance circuits extends to > 50 MHz (CMOS), > 500 MHz (bipolar) or even to > 1GHz (GaAs) so that the design of high-frequency continuous-time telecommunication circuits becomes feasible. In addition, the wider useful bandwidth of transconductances coupled with the reduced effects of circuit and device parasitics on filter performance result in far higher operating frequencies at which the circuits can function. The proposed circuit presented in the paper was tested in SPICE using 0.5μm CMOS process parameters provided by MOSIS (AGILENT) and the results thus obtained were in accordance with the theoretical values.

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ABSTRACT: Designing MIMO-OFDM using fixed sphere decoding detection method is implemented. The design includes OFDM-Transmitter and receiver sending 4 signals from transmitter to receiver with fixed sphere decoding detection method. In this paper OFDM-Transmitter process is implemented using xilinix software. In transmitter process, includes 16 QAM,IFFT . Four signals with 16 sample values are send for transmitter . In IFFT radix 4 _16 point is used, it reduces computational complexity. In the proposed system fixed sphere decoding detection method is used in receiver section ,we can achieve a fast detection approach for OFDM receiver-will detect the received signals quickly.FSD advantages is that no of visited nodes will be same for Hard and Soft output hence they have same throughput.

[1] K. W. Wong, C. Y. Tsui, R. S. K. Cheng, and W. H. Mow, "A VLSIarchitecture of a K-best lattice decoding algorithm for MIMO channels,"in Proc. IEEE Int. Symp. Circuits Syst., vol. 3. May 2002, pp. 273–276.

[2] Z. Guo and P. Nilsson, "Algorithm and implementation of the K-best sphere decoding for MIMO detection," IEEE J. Sel. Areas Commun.,vol. 24, no. 3, pp. 491–503, Mar. 2006.

[3] Markus Myllylä, Joseph R. Cavallaro, and Markku Juntti " Architecture Design and Implementation of the Metric First List Sphere Detector Algorithm", may 2011.

[4] H.-L. Lin, R. C. Chang, and H. Chan, "A high-speed SDM-MIMO decoder using efficient candidate searching for wireless communication,"IEEE Trans. Circuits, Syst. II, vol. 55, no. 3, pp. 289–293, Mar. 2008.

[5] M. Shabany and P. G. Gulak, "A 675 Mb/s, 4 × 4 64-QAM K-best MIMO detector in 0.13 μm CMOS," IEEE Trans. Very Large ScaleIntegr. (VLSI) Syst., vol. 20, no. 1, pp. 135–147, Jan 2012.

[6] Pankaj Bhagawat, Rajiballav Dash and Gwan Choi "Systolic Like Soft Detection Architecture for 4x4 64 –QAM MIMO System".2009
[7] Pei-Yun Tsai, Wei –Tzuo Chen, Xing-cheng Lin and Meng –Yuan Huang "A 4X4 64-qam Reduced- complexity K –best MIMO Detector upto 1.5 Gbps".