Abstract: Parallel counters are enter components in numerous number juggling circuits, particularly quick multipliers. Another paired counter plan is proposed. It utilizes Multiplexer (MUX) based full adder circuit, which aggregate the greater part of the "1" bits together. In proposed structure one xor obstruct in traditional snake is supplanted by multiplexer square with the goal that the basic way delay is limited. Counter-based systems have been proposed for use in worked in test set installing. A solitary counter or various counters might be utilized with one or different seeds.......
Keywords: Multiplexer, Counter, Full adder, Fault tolerant, stacking, Read Only Memory (ROM);
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