iosr-JVSP   Volume-4 ~ Issue-6 ~ Nov-Dec 2014

ABSTRACT: Field Programmable Gate Arrays (FPGA) provide very good hardware design flexibility. This paper specifies the generation of PWM signals for variable duty cycles using VHDL. Pulse Width Modulation found in large number of applications as a voltage controller. It is used in controlling output voltage of inverter in most of the applications.PWM has a fixed frequency and a variable voltage.

[1]. Koutroulis E., Dollas A. and Kalaitzakis K., "High-frequency pulse width modulation implementation using FPGA and CPLD ICs", Journal of Systems Architecture, Vol.52 (2006): pp. 332–344.
[2]. Rahim N.A. and Islam Z., "Field Programmable Gate Array-Based Pulse-Width Modulation for Single Phase Active Power Filter", American Journal of Applied Sciences, Vol.6 (2009): pp. 1742-1747.
[3]. Retif J.M., Allard B., Jorda X. and Perez A., "Use of ASICs in PWM techniques for power converters", Proceedings of the International Conference on Industrial Electronics, Control and Instrumentation, IEEE Xplore Press, Maui, HI, USA.,(1993) pp: 683-688.

ABSTRACT: The increasing growth of sub – micron technology has resulted in shrinking of the device size leading to increase in device density. In the modern System-on-a-Chip (SoC) design, many cores are integrated into a single chip, some of them are embedded. This increases the functional complexity of the chip. The internal sub – circuits of the chip cannot be accessed directly from the primary inputs of the chips. So the testing of the chip is becoming very time consuming and costly. Such SoC designs make the test of these embedded cores become a great challenge. Thus Automatic Testing Equipments (ATE) is becoming costly process for testing. To reduce the cost of testing the chips, Built in Self Test (BIST) has emerged as an cheaper alternative. BIST is a design technique that allows the chip to test itself. In this paper, the BIST is implemented on UART using Verilog. The simulation and synthesis of the design are performed using ModelSim SE PLUS 6.5 simulator and XILINX ISE 14.5 synthesis tool.
Keywords: ATE, BIST, BILBO, Power Analysis, UART.

[1]. Nitin Patel; Naresh Patel, 4 July 2013. VHDL Implementation of UART with BIST capability. Computing, Communications and Networking Technologies (ICCCNT),2013 Fourth International Conference. [2]. WAKHLE, G.B; AGGARWAL, I. ; GABA, S., 4 JUNE 2012. SYNTHESIS AND IMPLEMENTATION OF UART USING VHDL CODES. COMPUTER, CONSUMER AND CONTROL (IS3C), 2012 INTERNATIONAL SYMPOSIUM.
[3]. M.D. Mamun, M.S. Amin and J. Jalil, Single Core Hardware Modeling of Built-in-Self-Test for System on Chip Design, Research Journal of Applied Sciences Engineering and Technology, 4(7): 819-824, 2012
[4]. Shikha Kakar; Balwinder Singh ; Arun Khosla, 3, May 2009. Implementation of BIST Capability using LFSR Techniques in UART. International Journal of Recent Trends in Engineering ,Vol 1, No 3
[5]. Mohd.Yamani Idna Idris,Mashkuri Yaacob,Zaidi Razak. A VHDL Implementation of UART Design With BIST capability. Faculty of Computer Science and Information Technology,University of Malaya,50603 Kuala Lumpur,Malaysia.

ABSTRACT: This paper describes flash ADC design using linearity improved threshold quantized comparator. Here, the need for a reference voltage generation network has been eliminated in a 4 bit flash ADC; with completely digital cell based comparators. Output generated from comparator called thermometer code is related mathematically with binary conversion. This conversion property is used for mathematical modeling and complexity reduction of decoder circuitry by semi-parallel structuring of comparators. Circuit is designed in 250nm technology and it exhibits satisfactory performance even in temperature and process variation.
Keywords: Flash ADC, threshold, thermometer code, multiplexer, encoder, algebraic

[1]. Yoo, Jincheol, Kyusun Choi, and Daegyu Lee. "Comparator generation and selection for highly linear CMOS flash analog-to-digital
converter." Analog Integrated Circuits and Signal Processing 35.2-3 (2003): 179-187.
[2]. D.Lee,et al., "Design method and automation of comparator generation for flash A/D converter,"ACM Portal, No.5,2004,pp.127 -
155.
[3]. Tangel, Ali, and Kyusun Choi. ""The CMOS Inverter" as a comparator in ADC designs." Analog Integrated Circuits and Signal
Processing 39.2 (2004): 147-155.
[4]. H.Farkhani,M. Meymandi-Nejad and M. Sachdev, "A Fully Digital ADC Using a New Delay Element with enhanced Linearity",
IEEE International Symposium on Circuits and systems, ISCAS,18-21 May 2008,pp.2406-2409.
[5]. H. Chen, B. Song and K.Bacrania, "A 14-b 20-M Samples CMOS pipelined ADC with 1.8 V Power Supply," IEEE, Journal of
Solid-State Circuits, Vol.6,2001,pp.997-1001.

ABSTRACT: Array of antennas or sensors is widely used in many applications like communication, Rader, Sonar, Speech Processing and etc. Advantages of such system are higher degree of freedom, Adoption, Redundancy, Flexibility and etc. In real world the signals received by the array not only consist of desired signal but also consists the interferences from the sources in the surrounding environment. It is essential to remove the interfering signal and increase the Signal-to-Interference plus Noise Ratio (SINR) of the desired signal. Interference degrades the performance of the system and reduces the Detection and Estimation of the desired signal in the received signal. The goal of this Paper is to find the behaviour of LMS and RLS for different set of interfering signal, and to find the interference cancellation capability of the algorithms, and Comparison between the algorithms.

Keywords: Adaptive filter, Least mean square Algorithm, Recursive least square Algorithm.

[1]. R.H. Kwong, E.W. Johnston, "A Variable Step Size LMS Algorithm, IEEE Transactions on Signal Processing", Vol. 40, No. 7, pp.
1633-1642, July 1992.
[2]. Z. Tian, K. L. Bell, and H. L. Van Trees, "A recursive least squares implementation for adaptive beam forming under quadratic
constraint," In 9th IEEE Workshop, Signal Array Processing, Portland, pp. 9 –12, Sept. 1986.,
[3]. O. L. Frost, "An algorithm for linearly constrained adaptive array processing," Proc. IEEE, vol. 60, pp. 926 –935, Aug. 1972.
[4]. L. J. Griffiths and C. W. Jim, "An alternative approach to linearly constrained adaptive beam forming," IEEE Trans. Antennas
Propagat., vol.30, pp. 27–34, Jan. 1982
[5]. Y. Der Lin and Y. Hen Hu," Power-line interference detection and suppression in ECG signal Processing," IEEE Trans. Biomed.
Eng., vol.55, pp. 354-357, Jan.2008
[6]. R. H. Kwong and E. W. Johnston "A variable step size LMS algorithm", IEEE Trans. Signal Process., vol. 40, no. 7, pp.1633 -
1642, March1992

ABSTRACT:Shot change detection is an essential step in video content analysis. The field of Video Shot Detection (VSD) is a well exploited area. In the past, there have been numerous approaches designed to successfully detect shot boundaries for temporal segmentation. In this paper we present a procedure to detect and automatically classify Video shots. We present a method to detect shots using optic flow, and a method to classify the shot change into Abrupt/Hard cut or Gradual Transition using Robust Pixel Based Method.

Keywords: Video Shot Detection, Shot Boundary Detection, Optic Flow, Corner Detection,Automatic classification.

[1] R. Zabih, J. Miller, and K. Mai, "A feature-based algorithm for detecting and classifying scene breaks," in Proc. ACM Multimedia, 1995, pp. 189–200
[2] Comparison of Automatic Shot Boundary Detection Algorithms , Rainer Lienhart1 Microcomputer Research Labs, Intel Corporation, Santa Clara. 2004
[3] Video Shot Boundary Detection Based On Color Histogram.,Jordi Mas, Gabriel Fernandez .Digital Television Center,Spain. 2005
[4] Video Shot Meta-segmentation Based On Multiple Criteria For Gradual Transition Detection,efthymia Tsamoura, Vasileios Mezaris, Ioannis Kompatsiaris,Centre for Research and Technology Greece. 2008
[5] A Svm-based Soccer Video Shot Classification Department of Computer Science, Beijing Institute of Technology, Beijing , 2005,Yi-hua Zhou, Yuan-da Cao, Long-fei Zhang, Hong-xin Zhang
[6] Shot View Classification for Playfield-based Sports Video, Alfian Abdul Halin, Mandava Rajeswari, Dhanesh Ramachandram Computer Vision Lab , Penang, Malaysia , 2009

ABSTRACT: Protecting privacy for exchanging information through the media has been a topic researched by many people. This work presents a security solution for transmitting fingerprint images over insecure channels. Here security is provided by an encryption technique based on reversible hidden transform (RHT), fractional wavelet packet transform (FrWPT), chaotic map and singular value decomposition (SVD). This scheme proposes the use of coupled two-dimensional piecewise nonlinear chaotic map (CTPNCM) for selecting the transform order of FrWPT. And here the inputs to this chaotic map act as the secret keys. By architecture itself this nonlinear chaotic map provides more security to the encryption scheme than the linear ones.

[1]. Gaurav Bhatnagar "Chaos-based security solution for fingerprint data during communication and transmission", IEEE transactions
on instrumentation and measurement, vol 61, no 4, April 2012
[2]. U. Uludag, S. Pankanti, and S. Prabhakar, "Biometrics cryptosystems: Issues and challenges," Proc. IEEE, vol. 92, no. 6, pp. 948–
960, Jun. 2004.
[3]. A. K. Jain, L. Hong, S. Pankanti, and R. Bolle, "An identity-authentication system using fingerprints," Proc. IEEE, vol. 85, no. 9,
pp. 1365–1388, Sep. 1997.
[4]. A. J. Menezes, P. C. Van Oorschot, and S. A. Vanstone, "Handbook of Applied Cryptography", Boca Raton, FL: CRC Press, 1996.
[5]. D. Moon, Y. Chung, S. B. Pan, K. Moon, and K. I. Chung, "An efficient selective encryption of fingerprint images for embedded
processors," ETRI J., vol. 28, no. 4, pp. 444–452, Aug. 2006.
[6]. C. Ashok Narayanan, k.M.M Prabu, "The fractional fourier transform: theory, implementation and error analysis", Elsevier J.,June
2003, pp. 511-521

ABSTRACT: There is a great need and demand for high throughput biomedical data display system in every clinical study and diagnostic labs in Hospitals. To cater to this demand, we have designed FPGA-based memory architecture suitable for use in displaying low frequency EEG data. Memory architecture is designed to acquire up to 32 channel EEG data. An Instrumentation amplifier suited for EEG signals has also been designed and tested for a single channel bipolar configuration. The implemented memory architecture has fast retrieval time and a large data storage capacity.

[1]. Mohammed Abdullah, Member, Omar Elkeelany, and Ali T. Alouani, " A Low-Cost Stand-Alone Multichannel Acquisition, Monitoring, and Archival System with On-Chip Signal Preprocessing", IEEE transactions on Instrumentation and Measurement, Vol. 60(8), Aug. 2011.
[2]. K. Arshak, A. Arshak, E. Jafer, D. Waldern, and J. Harris, "Low-power wireless smart data acquisition system for Monitoring Pressure in medical application, Microelectron. Int., Vol. 25(1), pp. 3-14, 2008.
[3]. J. M. Cardoso, J. B. Simões, and C. M. B. A. Correia, " A high performance reconfigurable hardware platform for Digital pulse", IEEE Trans. Nucl. Sci., Vol. 51(3), pp. 921–925, Jun.2004.
[4]. Custódio F. M. Loureiro and Carlos M. B. A. Correia, "Innovative Modular High-Speed Data-Acquisition Architecture",IEEE transactions on nuclear science, Vol. 49(3), June 2002.
[5]. Croft RJ, Barry RJ, "Removal of ocular artefact from the EEG: a review", Journal of Clinical Neurophysiology, Vol. 30(1), pp .5-19, 2000.
[6]. Xicai Yue, Emmanuel M. Drakakis, Mayasari Lim, Anna Radomska, Hua Ye, Athanasios Mantalaris, Nicki Panoskaltsis, and Anthony Cass A, "Real-Time Multi-Channel Monitoring System for Stem Cell Culture Process", IEEE transactions on Biomedical circuits and systems, Vol. 2(2), June 2008.

ABSTRACT: Image processing is an important component of modern technologies as it provides the improvement in pictorial information for human interpretation and processing of image data for storage, transmission and representation autonomous machine perception. This paper focused on image restoration which is sometimes referred to image deblurring and filtering. Image restoration is concerned with the reconstruction of blur parameters of the uncorrupted image from a blurred and noisy one. Image deblurring refers to procedures that attempt to reduce the blur amount in a blurry image and grant the degraded image an overall sharpened appearance to obtain a clearer image. In this paper, the various kind of noise are added and then deblurring process is used to obtain a blurred image. After this image filtering is also implemented for removing these noise.

KeyWords: deblurring,image degradation, MSE,PSNR

[1] Sonia Saini, and LalitHimral, "Image processing using blind deconvolution deblurring Technique" , International Journal of Applied Engineering and Technology ISSN: 2277-212X (Online) An Open Access, Online International Journal Available at http://www.cibtech.org/jet.htm 2014 Vol. 4 (2) April-June, pp.115-124/S.
[2] Mr. RohitVerma, Dr. Jahid Ali, "A Comparative Study of Various Types of Image Noise and Efficient Noise Remov-al Techniques" International Journal of Advanced Research in Computer Science and Software Engineering 3(10), October – 2013.
[3] Image Restoration Technique with Non Linear Filter CharuKhare and Kapil Kumar Nagwanshi International Journal of Advanced Science and Technology Vol. 39, February, 2012.
[4] Zohair Al-Ameen, GhazaliSulong, and Md. Gapar Md. Johar, "International Journal of Advanced Science and Technology",Vol. 44, July, 2012, A Comprehensive Study on Fast image Deblurring Techniques.