iosr-JVSP   Volume-4 ~ Issue-6 ~ Nov-Dec 2014

ABSTRACT: Segmentation is a fundamental process in digital image processing which has found extensive applications in areas such as medical image processing, compression, diagnosis arthritis from joint image, automatic text hand writing analysis, and remote sensing.The clustering methods can be used to segment any image into various clusters based on the similarity criteria like color or texture. In this research we have developed a method to segment color images using K-means clustering algorithm. K-means clustering algorithm divides the image into K clusters based on the similarity between the pixels in that cluster. In this research we have used Euclidean distance formula to define clusters in K-mean clustering. The proposed method has been applied to a variety of images and conclusions have been drawn.

Keywords: Clustering, Color Space, Image Segmentation,Indexing, K-Means Algorithm

[1]. McAndrew, An Introduction to Digital Image Processing with Matlab, Victoria University of Technology.
[2]. M. Sahu and D. K. Parvathi, "Segmentation of Colour Data Base Image by Implementing K-means Clustering," International Journal of Innovations in Engineering and Technology, vol. 2, no. 4, pp. 229-234, August 2013.
[3]. M. Lalitha, M. Kiruthiga and C. Loganathan, "A Survey on Image Segmentation through Clustering Algorithm," International Journal of Science and Research, vol. 2, no. 2, pp. 348-358, February 2013.
[4]. R. Jipkate and D. V. V. Gohokar, "A Comparitive Analysis of Fuzzy C-means Clustering and K-means Clustering Algorithms," International Journal of Computationsl Engineering, vol. 2, no. 3, pp. 737-739, May-June 2012.
[5]. R. A. Barakbah and Y. Kiyoki, "A New Approach for Image Segmentation using Pillar-K-means Algorithm," World Academy of Science, Engineering and Technology, pp. 23-28, 2009.

ABSTRACT:In the process of medical image retrieval, the representing features define the retrieval accuracy. The representing features are described by various definitions, one is the shape. The shape representation of an observation made reveals various effects in the observing individual. In this paper to improve the accuracy of shape based feature extraction and retrieval is developed. This paper presents a new modified approach for shape feature representation in a 1-D representation and decomposition for a closed bounding region extraction for contour coding. This coding develops a new retrieval system for shape based retrieval system.

Keyword: Medical image retrieval, contour coding, 1-D representation, spectral coding.

[1]. Yiping Liu, Hui Liu, Zuowei Zhao, Lina Zhang, Xiang Liu, "A new active contour model-based segmentation approach for Accurate extraction of the lesion from breast DCE-MRI", ICIP, IEEE, 2013.
[2]. H. Imran, S. Vikash, and K. S. Vivek, "Review on offline signature verification methods based on artificial intelligence technique," International Journal of Advancements in Research & Technology, vol. 2, no. 5, pp. 383–388, 2013.
[3]. G. Zhang, Z. Ma, L. Niu, and C. Zhang, "Modified Fourier descriptor for shape feature extraction," Journal of Central South University, vol. 19, no. 2, pp. 488–495, 2012.
[4]. B. Zhong andW. Liao, "Direct curvature scale space: theory and corner detection," IEEE Transactions on Pattern Analysis and Machine Intelligence, vol. 29, no. 3, pp. 508–512, 2007.
[5]. Y. Cui and B. Zhong, "Shape retrieval based on parabolically fitted curvature scale-space maps," in Intelligent Science and Intelligent Data Engineering, vol. 7751 of Lecture Notes inComputer Science, pp. 743–750, 2013.
[6]. Y. Gao, G. Han, G. Li, Y.Wo, and D.Wang, "Development of currentmoment techniques in image analysis," Journal of Image and Graphics, vol. 14, no. 8, pp. 1495–1501, 2009.

ABSTRACT: A new algorithm has been developed for feature based corner detection for mosaicing images. Using this algorithm, a novel architecture suitable for FPGA/ASIC implementation has also been designed. The feature based corner detection technique proposed here is for extracting accurate corner positions than unstable corner points in existing algorithms. The design has been coded in Verilog conforming to RTL coding guidelines and fits in a single FPGA chip. The proposed design incorporates a high degree of pipelining and parallelism and hence offers high throughputs. The algorithm has also been coded in MATLAB in order to validate the hardware results. The Verilog design of the feature based corner detection architecture has been targeted on Xilinx Spartan6 xc6slx45-3fgg676 FPGA device. The design utilizes about 12,198 slices (58%) and the operating frequency is maximum of 292 MHz. The performance parameter PSNR has been computed for both the proposed and the existing methods for many number of mosaic images. The proposed method offers better reconstructed image quality and is 35 dB or more. Keywords: Corner detection, Gradient Operator, Architecture, FPGA, Verilog

1]. Marko Heikkila and Matti Pietikainen, "An Image Mosaicing module for Wide–Area Surveillance", VSSN'05, November 11, 2005, Singapore, ACM 1-59593-242-9/05/0011.
[2]. B. Zitova and J. Flusser, "Image registration methods: a survey", Image and vision Computing, (21):977-1000, 2003, doi:10.1016/S0262-8856(03)00137-9.
[3]. Nabeel Shirazi, M. Athansa and A.Lynn abbott, "Implementation of a 2-D Fast Fourier Trasform on FPGA based Custom Computing Machine", Proceedings of 12th Reconfigurable Architecture Workshop, Denver 2005.
[4]. M. Brown and D. Lowe, "Automatic panoramic image stitching using invariant features", Intl. J. of Computer Vision, pp. 59–73, 2007.
[5]. Alistair J Fitch, "Fast Robust Correlation", IEEE Transactions on Image Processing, Vol. 14, No. 8, August 2005.
[6]. Y D Zhang, L. N. Wu Wang, "Improved Walsh images interpolation method", Computer Engineering & Applications 2011, 47(9): 156-159.

ABSTRACT:A power-gating scheme was presented to support multiple power-off modes and reduce the leakage power during short periods of inactivity. However, this scheme can suffer from high sensitivity to process variations, which impedes manufacturability. Recently power-gating technique are used for increasing power efficiency however, they are sensitive to process variations and having more wake up time. The proposed power gating scheme is tolerant to process variations and scalable to more than two intermediate power-off modes. The proposed design requires less design effort and offers greater power reduction and smaller area cost than the previous method. In addition, it can be combined with existing techniques to offer further static power reduction benefits. Analysis and extensive simulation results demonstrate the effectiveness of the proposed design.
Index Terms: Leakage power, Multi-mode VTCMOS switches, Power Consumption reduction, process variation, Reconfigurable power-gating structure.

[1]. Semiconductor Industry Association. (2007) [Online]. Available:http://www.itrs.net/Links/2007ITRS/Home2007.htm
[2]. D. Lackey, P. Zuchowski, T. Bednar, D. Stout, S. Gould, and J. Cohn, ―Managing power and performance for system-on-chip designs using voltage islands,‖ in Proc. IEEE/ACM Int. Conf. Comput. Aided Design, Nov. 2002, pp. 195–202.
[3]. R. Puri, D. Kung, and L. Stok, ―Minimizing power with flexible voltage islands,‖ in Proc. IEEE Int. Symp. Circuits Syst., May 2005, pp. 21–24.
[4]. R. Puri, L. Stok, J. Cohn, D. Kung, D. Pan, D. Sylvester, A. Srivastava, and S. Kulkarni, ―Pushing ASIC performance in a power envelope,‖ in Proc. Design Autom. Conf., Jun. 2003, pp. 788–793.
[5]. [K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, ―Leakage current mechanisms and leakage reduction techniques in deepsubmicrometer CMOS circuits,‖ Proc. IEEE, vol. 91, no. 2, pp. 305–327, Feb. 2003.
[6]. S. Idgunji, ―Case study of a low power MTCMOS based ARM926 SoC: Design, analysis and test challenges,‖ in Proc. IEEE Int. Test Conf., Oct. 2007, pp. 1–10.

ABSTRACT: Sundram finance play a vital role in resource mobilization and its efficient allocation to the productive sources of the economic system. In this process of development, sundram financehave emerged as strong financial intermediaries and are playing an important role in bringing stability to the financial system and efficiency to the resource allocation process. Sundarm finanance groups are essentially financial intermediaries. They have become a critical link among various financial segments in the economy. Today, they play a crucial role in the mobilization of resources, especially from small savers. On account of the huge resources at their disposal, they have also emerged as the dominant players in the capital market. With such enormous funds at their disposal is hardly surprising that they have become critical players in the market. The company operates through a network of 581 branches. structure.

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ABSTRACT: Under water systems use processor based rooted systems to provide control and guidance to the under water vehicles. They obtain target and vehicle dynamics data from sensors and gyros, and process this data as per control and guidance algorithms to generate control and guidance parameters to the actuation system. Traditionally x86 families are being used in these systems in amassing to memory, I/Os and other peripherals being on the card. The recent developments in FPGA (Field Programmable Gate Array) technology has made pavement to use superior FPGAs with IP cores to develop under water systems. The modern FPGA devices include 32-bit Power PC processor, memory blocks and programmable area to comprise peripheral blocks. Under water systems developed out of the FPGA cores are definitely have several advantages like, saving the card size (FPGA accommodates several of the components in addition to the processor), flexibility to adopt changes in design (as FPGA can be programmed by the end user), preventing obsolescence of components. Building an under water systems based on FPGA IP cores is an innovative and hottest technological demonstration with several advantages to prophesy. The present work describes the dwindling in power consumption and size of the Under Water System.

[1]. http://www.fpgadeveloper.com/2008/04/timer-with-interrupts.html
[2]. http://forums.xilinx.com/xlnx/board/message?board id=EDK&thread.id=12471
[3]. http://www.xilinx.com/ise/embedded/edk_docs.htm.
[4]. http://www.eda- publishing.org/ewme2008/htmls/Pdfs/P209.pdf.
[5]. http://www.xilinx.com/ipcenter/
[6]. http://www.cse.sc.edu/~gquan/CSCE313/Docs/Lab2. Pdf.
[7]. http://www.mte-india.com/DownloadNew.aspx#.
[8]. http://www.xilinx.com/support/documentation/White_papares/wp213.pdf.

ABSTRACT: This paper proposes a built-in self-detection and correction (BISDC) architecture for motion estimation computing arrays(MECAs).Based on the error detection & correction concepts of bi-residue codes, any single error in each processing element in an MECA can be effectively detected and corrected online using the proposed BISD and built-in self-correction circuits. Performance analysis and evaluation demonstrate that the proposed BISDC architecture performs well in error detection and correction with minor area.

Keywords: Built-in self-detection and correction (BISDC), Block Matching Motion Estimation (BME) algorithm, Digital Video Compression, Motion estimation computing arrays (MECA), video coding standard

[1]. Advanced Video Coding for Generic Audiovisual Services, ISO/IEC 14496-10:2005 (E), Mar. 2005, ITU-T Rec. H.264 (E).
[2]. Information Technology-Coding of Audio-Visual Objects—Part 2: Visual, ISO/IEC 14 496-2, 1999.
[3]. Y. W. Huang, B. Y. Hsieh, S. Y. Chien, S. Y. Ma, and L. G. Chen, ―Analysis and complexity reduction of multiple reference frames motion estimation in H.264/AVC,‖ IEEE Trans. Circuits Syst. Video Technol., vol. 16, no. 4, pp. 507–522, Apr. 2006.
[4]. C. Y. Chen, S. Y. Chien, Y. W. Huang, T. C. Chen, T. C. Wang, and L. G. Chen, ―Analysis and architecture design of variable block-size motion estimation for H.264/AVC,‖ IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 3, pp. 578–593, Mar. 2006.
[5]. T. H. Wu, Y. L. Tsai, and S. J. Chang, ―An efficient design-for-testability scheme for motion estimation in H.264/AVC,‖ in Proc. Int. Symp VLSI Design, Autom. Test, Apr. 2007, pp. 1–4.
[6]. M. Y. Dong, S. H. Yang, and S. K. Lu, ―Design-for-testability techniques for motion estimation computing arrays,‖ in Proc. Int. Conf. Commun., Circuits Syst., May 2008, pp. 1188–1191.
[7]. Y. S. Huang, C. J. Yang, and C. L. Hsu, ―C-testable motion estimation design for video coding systems,‖ J. Electron. Sci. Technol., vol. 7, no.4, pp. 370–374, Dec. 2009.