iosr-JVSP   Volume-5 ~ Issue-1 ~ Jan-Feb 2015

ABSTRACT: High integration density, low power and fastperformance are all critical parameters in designing of memory blocks. Static Random Access Memories (SRAMs)'s focusing on optimizing dynamic power concept of virtual source transistors is used for removing direct connection between VDD and GND. Also stacking effect can be reduced by switching off the stacktransistors when the memory is ideal and the leakage current using SVL techniques This paper discusses the evolution of 9t SRAM circuits in terms of low power consumption, The whole circuit verification is done on the Tanner tool, Schematic of the SRAM cell is designed on the S-Edit and net list simulation done by using T-spice and waveforms are analyzed through the W-edit.

Keywords: Leakage Current; Low Power; SRAM; Stack tech; SVL; VLSI; USVL; LSVL; VTCMOS; MTCMOS.

[1]. ShyamAkashe, Meenakshi Mishra, and Sanjay Sharma, Self controllable voltage level circuit for low power, high speed 7TSRAM cell at 45nm
[2]. Design Of Efficient Low Power 9t Sram Cell , K.Gavaskar1 S.Priya2 1P.G Scholar/VLSI Design, 2Assistant professor ECE,Bannari Amman Institute of Technology Sathyamangalam, India. Vol. 2 Issue 1, January- 2013-(IJERT)
[3]. Performance Evaluation of Different SRAM Schemes in 16nm Predictive Technology, Swati Vijayvergia Vol. 4 Issue 10, January- 2013-(IJERT)
[4]. A.J. Bhavnagarwala, X. Tang, and J. Meindl,\The simpact of Intrinsic Device Fluctuations on CMOS SRAM Cell Stability," IEEE Journal of Solid State Circuits, vol. 36, No. 4, pp. 658-665,April 2001.
[5]. Leakage Reduction and Stability Improvement Techniques of 10t SRAM Cell: A Survey A.VeeraLakshmi, S.Priya, (IJITEE) ISSN: 2278-3075, Volume-3, Issue-7, December 2013.
[6]. Design a 5T SRAM by using self controllable voltage level leakage reduction technique with CMOS Technology Laxmi Singh1, Ajay Somkuwar2 1Department of Electronics & Communication, Corporate college
[7]. of Technology, Bhopal, INDIA. 2Department of Electronics & Communication Bhopal, MP, INDIA .

ABSTRACT:This paper is base on the implementation of Reduce Instruction set computer with the application of Discrete Cosine transform (DCT) , Inverse DCT, Discrete Fourier Transform (DFT) and Fast Fourier Transform (FFT), Digital filter are performed by DSP system. Digital filter is one of the important contents of digital signal process. The performance of the processor design is improved by using the pipeline approach. It allows the processor to work on different steps of the instruction at the same time, thus more instruction can be executed in a shorter period of time. The analysis of this processor will provide various features including arithmetic operations. The speed of operation is mainly affected by the computational complexity due to multipliers and adder modules of the digital systems. Our work will targets the computer architecture courses and presents an FPGA (Field Programmable Gate Array) implementation of a MIPS (Microprocessor without Interlocked Pipeline Stages) via VHDL (Very high speed integrated circuit Hardware Description Language) design. The latency and computational time is utmost important in microprocessor. Thus we design the multiplier and adder module with improve latency and computational time.

Keywords: IIR FILTER, FPGA, DSP Processor, VHDL

[1] Sheikh Md. Rabiul Islam, Robin Sarker, Shumit Saha, A. F. M. Nokib Uddin " Design of a programmable digital IIR filter based on FPGA" IEEE International Conference on Infonnatics, Electronics & Vision ICIEV year 2012.
[2] Amit Kumar Singh Tomar, Rita Jain "20-Bit RISC & DSP System Design in an FPGA" IEEE international conference in year 2013.
[3] Chaohua Dai, Weirong Chen, and Yunfang Zhu "Seeker Optimization Algorithm for Digital IIR Filter Design" IEEE Transactions On Industrial Electronics, Vol. 57, No. 5, May 2010 pp no. 1710.
[4] ZHANG Jian-ping, PAN Ling-ling, DING Quan-fei "IIR Digital Filter Design Based on DSP and SOPC" International Symposium on Intelligence Information Processing and Trusted Computing year 2010.

ABSTRACT: Segmentation technique plays a major role in scripting the documents for extraction of various features. Many researchers are doing various research works in this field to make the segmenting process simple as well as efficient. In this paper a simple segmentation technique for both the line and word segmentation of a script document has been proposed. The main objective of this technique is to recognize the spaces that separate two text lines.For the Word segmentation technique also similar procedure is followed. In this work ,three different scanned document have been taken as input images for both line and word segmentation techniques. The results found were outstanding with average accuracy for both line and word. It provides 100% accuracy for line segmentation and 100% for line segmentation as well. Evaluation results show that our method outperforms several competing methods.

Key Words: Segmentation, Line Segmentation, Word Segmentation, Devanagiri Script, Machine learning, shirorekha, white rows, white columns, consecutive white rows (CWR) threshold

[1]. Vikash J Dhongre, Vijay H Mankar, "International Journal Of Computer Science, Engineering and information Technology(IJCSEIT)",Vol 1,No.3,August 2011
[2]. Naresh Kumar Garg, Lakhwinder Kaur, M. K. Jindal, "International journal of computer Applications(0975-8887)",Volume 1-No.- 4,2010
[3]. Nallapareddy Priyanka, Srikanta Pal, Ranju Mandal, (2010) "Line and Word Segmentation Approach for Printed Documents", IJCA Special Issue on Recent Trends in Image Processing and Pattern Recognition-RTIPPR, pp 30-36
[4]. Raghuraj Singh, C. S. Yadav, Prabhat Verma, "Optical Character Recognition (OCR) for Printed Devnagari Script Using Artificial Neural Network", International Journal of Computer Science & Communication, 2010.
[5]. M. K. Jindal, R. K. Sharma and G. S. Lehal, "Structural Features for Recognizing Degraded Printed Gurmukhi Script", in Proceedings of the IEEE 5th International Conference on Information Technology: New Generations (ITNG 2008), pp. 668-673, April 2008.

ABSTRACT: Object tracking is a process devoted to locate the pathway of moving object in the succession of frames. The tracking of the object has been emerged as a challenging facet in the fields of robot navigation, military, traffic monitoring and video surveillance etc. In the first phase of contributions, the tracking of object is exercised by means of matching between the template and exhaustive image through the Normalized Cross Correlation (NCCR). In order to update the template, the moving objects are detected using frame difference technique at regular interval of frames. Subsequently, NCCR or Principal Component Analysis (PCA) or Histogram Regression Line (HRL) of the template and moving objects are estimated to find the best match to update the template. The second phase discusses the tracking of object between the template and partitioned image through the NCCR with reduced computational aspects. However, the updating schemes remain same. Here, an exploration with varied bench mark dataset has been carried out. Further, the comparative analysis of the proposed systems with different updating schemes such as NCCR, PCA and HRL has been succeeded. The offered systems considerably reveal the capability to track an object indisputably under diverse illumination conditions.

Keywords: Centroid, Frame difference, Histogram Regression Line, Normalized Cross Correlation, Template updating, Object Tracking

[1]. A.Yilmaz, O.Javed and M.Shah, Object tracking: A survey, ACM, Computing Surveys, 38, 4, Article 13, Dec. 2006.
[2]. Y. D. Xu. Richard, G. A. John and S. J. Jesse, Robust real time tracking of non-rigid objects, Proceedings of the Pan-Sydney area
workshop on Visual information processing, Australia, June, 2004, pp.95-98.
[3]. I. Haritaoglu, D. Harwood and L. Davis, W4: real time surveillance of people and their activities, IEEE Trans. Patt. Analy Mach.
Intell. 22, 8, 2000, pp.809–830.
[4]. L. Wang, W. Hu and T. Tan, Face tracking using motion guided dynamic template matching, Proceedings of the 5th Asian
Conference on Computer Vision -ACCV2002, Melbourne, Australia, January, 2002, pp.1-6
[5]. J.P. Lewis, Fast Normalized Cross-Correlation, Vision Interface, 1995, pp.120-123.

ABSTRACT: This paper presents the modeling and simulation of a 833.33 kS/s, 51.279μW successive approximation register(SAR) Analog to Digital Converter(ADC) using 0.18μm CMOS technology that uses internally generated signal for approximation for low power applications. The ADC is powered by single supply voltage of 1V. In our scheme, comparator output time and bit settling time of the Digital to Analog Converter(DAC) are utilized to generate a signal level such that the next step of the conversion can take place. This model is significant for Globally Asynchronous Locally Synchronous(GALS) system integration.

Keywords: Globally Asynchronous Locally Synchronous (GALS), Asynchronous ADC.

[1]. Harpe, P.J.A.; Zhou, C.; Yu Bi; van der Meijs, N.P.; Xiaoyan Wang; Philips, K.; Dolmans, G.; de Groot, H., "A 26 W 8 bit 10 MS/s Asynchronous SAR ADC for Low Energy Radios," Solid-State Circuits, IEEE Journal of , vol.46, no.7, pp.1585,1595, July 2011
[2]. S. Mukherjee, D. Saha, P. Mostafa, S. Chatterjee, C.K. Sarkar, A 4-bit Asynchronous Binary Search ADC for Low Power , High Speed Applications, International Synposium on elecronic System Design, 2012
[3]. Anh Tuan Do; Chun Kit Lam; Yung Sern Tan; Kiat Seng Yeo; Hao Cheong, Jia; Xiaodan Zou; Lei Yao; Kuang Wei Cheng; Minkyu Je, "A 160 nW 25 kS/s 9-bit SAR ADC for neural signal recording applications," New Circuits and Systems Conference (NEWCAS), 2012 IEEE 10th International , vol., no., pp.525,528, 17-20 June 2012
[4]. Chao Yuan; Lam, Y.Y.H., "A 281-nW 43.3 fJ/conversion-step 8-ENOB 25-kS/s asynchronous SAR ADC in 65nm CMOS for biomedical applications," Circuits and Systems (ISCAS), 2013 IEEE International Symposium on , vol., no., pp.622,625, 19-23 May 2013
[5]. C. Yuan and Y. Lam, "Low-energy and area-efficient tri-level switching scheme for SAR ADC," IET Electronics Lett.,vol. 48, no. 9, Apr. 2012

ABSTRACT:In modern high performance integrated circuits, maximum of the total active mode energy is consumed due to leakage current. SRAM cell array is main source of leakage current since majority of transistor are utilized for on-chip memory in today high performance microprocessor and system on chip designs. Therefore the design of low leakage SRAM is required. Reducing power dissipation, supply voltage, leakage currents, area of chip are the most important parameters in today`s VLSI designs. But scaling of these parameters will lead to drastic increase in sub threshold leakage currents and power dissipation because of that performance of the design is degraded. So to overcome these issues it is better to concentrate on reduction of active leakage currents and dynamic power dissipation by using power reduction techniques. In this paper 9T SRAM (data retention p-gated) cell for low voltage and energy constrain application is analyzed with respect to power dissipation, area and delay. The analyzed design of 9T SRAM cell with MTCMOS technique has been proposed. Designed circuits are simulated in Microwind 3.1 VLSI CAD Tool in 90 and 65nm CMOS technology.

Keywords - CMOS, 6T SRAM cell, 8T SRAM cell, 9T SRAM cell, MTCMOS, Low Power Consumption.

[1] CMOS Digital Integrated Circuits Analysis and Design Third Edition2003, By Sung-Mo Kang, Yusuf Leblebici.
[2] E. Grossar, M. Stucchi, K. Maex, W. Dehaene, "Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies," IEEE Journal of Solid-State Circuits, vol. 41, no. 11, pp.2577-2588, Nov. 2006.
[3] V. Gupta and M. Anis, "Statistical design of the 6T SRAM bit cell," IEEE Trans. Circuits Syst.- I, vol. 57, no. 1, pp. 93–104, Mar. 2010.
[4] R. E. Aly and M. A. Bayoumi, "Low-power cache design using 7T SRAM cell," IEEE Trans. Circuits Syst.- II, vol. 54, no. 4, pp. 318– 322, Apr. 2007.
[5] K. Kim, H. Mahmoodi, K. Roy, "A low-power SRAM using bit line charge recycling", IEEE journal of solid-state circuits, vo1. 43, no. 2, pp. 446-459, Feb. 2008.
[6] M. Anis, S. Areibi, M. Mahmoud, and M. Elmasry, "Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique," Proc. DAC, pp. 480-485, 2002.

ABSTRACT:Field Programmable Gate Arrays (FPGA) are increasingly being used to design high- end computationally intense microprocessors capable of handling both fixed and floating- point mathematical operations. Addition is the most complex operation in a floating-point unit and offers major delay while taking significant area. Over the years, the VLSI community has developed many floating-point adder algorithms mainly aimed to reduce the overall latency. The Objective of this paper to implement the 32 bit binary floating point adder with minimum time. Floating point numbers are used in various applications such as medical imaging, radar, telecommunications Etc. Here pipelined architecture is used in order to increase the performance and the design is achieved to increase the operating frequency. The logic is designed using VHDL. This paper discusses in detail the best possible FPGA implementation will act as an important design resource. The performance criterion is latency in all the cases. The algorithms are compared for overall latency, area, and levels of logic and analyzed specifically for one of the latest FPGA architectures provided by Xilinx.

Keywords: ASIC,FPGA,IEEE 754,pipelining,VHDL.

[1]. Ronald Vincent, Ms.Anju.S.L "Decimal Floating Point Format Based on Commonly Used Precision For Embedded System Applications." International Conference on Microelectronics, Communication and Renewable Energy (ICMiCR-2013).
[2]. Somsubhra Ghosh, Prarthana Bhattacharyya and Arka Dutta "FPGA Based Implementation of a Double Precision IEEE Floating-Point Adder", Proceedings of7'h International Conference on Intelligent Systems and Control (ISCO 2013).
[3]. Maarten Boersma, Michael Kr¨oner, Christophe Layer, Petra Leber, Silvia M. M¨uller, Kerstin Schelm "The POWER7 Binary Floating-Point Unit", 2011 20th IEEE Symposium on Computer Arithmetic.
[4]. Reshma Cherian, Nisha Thomas, Y. Shyju "Implementation of Binary to Floating Point Converter using HDL"P-461-P464.
[5]. Anand Mehta, C. B. Bidhul, Sajeevan Joseph, Jayakrishnan. P " Implementation of Single Precision Floating Point Multiplier using Karatsuba Algorithm", 2013 International Conference on Green Computing, Communication and Conservation of Energy (ICGCE).
[6]. Libo Huang, Li Shen, Kui Dai, Zhiying Wang "A New Architecture For Multiple-Precision Floating-Point Multiply-Add Fused Unit Design".

ABSTRACT:In this paper, we propose an algorithm for neighbors finding in images represented by quadtree data structure. We first present a scheme for addressing image pixels that takes into account the order defined on a quadtree blocks. We study various properties of this method, and then we develop a formula that establishes links between quadtree blocks. Based on these results, we present an efficient algorithm that generates the list of location codes of all possible neighbors, in all directions, for a given block of the quadtree. Keywords: Image processing, quadtree, neighbors finding, pixel ordering.

[1] H. Samet, "Neighbor finding in images represented by octrees," Comput. Vision, Graph. Image Process., vol. 46, no. 3, pp. 367–386, 1989.
[2] C.-Y. Huang and K.-L. Chung, "Faster neighbor finding on images represented by bincodes," Pattern Recognit., vol. 29, no. 9, pp. 1507–1518, 1996.
[3] G. Schrack, "Finding neighbors of equal size in linear quadtrees and octrees in constant time," CVGIP Image Underst., vol. 55, no. 3, pp. 221–230, 1992.
[4] J. Vörös, "A strategy for repetitive neighbor finding in images represented by quadtrees," Pattern Recognit. Lett., vol. 18, no. 10, pp. 955–962, 1997.
[5] R. A. Finkel and J. L. Bentley, "Quad trees a data structure for retrieval on composite keys," Acta Inform., vol. 4, no. 1, pp. 1–9, 1974.
[6] H. Samet, "Neighbor finding techniques for images represented by quadtrees," Comput. Graph. Image Process., vol. 18, no. 1, pp. 37–57, 1982.

ABSTRACT: Multiplier is an important building block in many electronic system design. There are many available methods and techniques for designing multipliers. Wallace multiplier is important and popular multiplier architecture. In this paper, design and analysis of a conventional Wallace multiplier is presented by using Cadence virtuoso in 180nm CMOS technology. Performance analysis in terms of power, delay, and power delay product are performed for a 4-bit Wallace multiplier in 180nm CMOS technology. The power and delay of the designed multiplier are 689.3μW and 50μs respectively.

Keywords: Delay, Multiplier, Power delay product, Power Dissipation, Wallace multiplier.

[1]. C. S. Wallace, A Suggestion for a Fast Multiplier, IEEE Transactions on Computers, 13, 1964,14-17.
[2]. E. E. Swartzlander, and R. S. Waters, A Reduced Complexity Wallace Multiplier Reduction, IEEE Transactions on Computers, 59, 2010, 1134-1137.
[3]. M. Kumar, M. A. Hussain, and S. K. Paul, Performance of a Two Input Nand Gate Using Subthreshold Leakage Control Techniques, Journal of Electron Devices, 14, 2012, 1161-1169.
[4]. M. Kumar, M. A. Hussain, and L. K. Singh, Design of a Low Power High Speed ALU in 45nm Using GDI Technique and its Performance Comparison, Communications in Computer and Information Science, Springer Berlin Heidelberg, 142, 2011, 458-463.
[5]. P.V. Rao, C. P. R. Prasanna, and S. Ravi, VLSI Design and Analysis of Multipliers for Low Power, IEEE Fifth International Conference on Intelligent Information Hiding and Multimedia Signal Processing, Kyoto, 2009, 1354-1357.
[6]. D. R. Gandhi, and N. N. Shah, Comparative Analysis for Hardware Circuit Architecture of Wallace Tree Multiplier, IEEE International Conference on Intelligent Systems and Signal Processing, Gujarat, 2013, 1-6.
[7]. K. G. Krishna, B. Santhosh, and V. Sridhar, Design of Wallace Tree Multiplier using Compressors, International Journal of Engineering Sciences & Research Technology, 2, 2013, 2249-2254.