iosr-JVSP   Volume-5 ~ Issue-1 ~ Jan-Feb 2015

ABSTRACT: This paper presents information on AES Encryption and Decryption for multi processors. In this paper AES algorithm is used. The AES algorithm is a round based algorithm. The round based algorithm is used to provide security to the information. In AES algorithm there are different types of keys, they are 128,192 and 256 bits. These bits are used to encrypt and decrypt the information. In this paper 128bits are used. In this paper the main functional blocks are key generation, encryption and decryption. In order produce a new key sub byte, rotate word, round constant and add round key operations are used. In order to convert plain text to cipher message the sub bytes, shift rows, mix column and add round key operations are used. By doing these operations the cipher information is obtained. This cipher will be given to the decryption and it is the total reverse process of encryption. After completion of reverse process the outcome is original information.

Index terms- Advanced Encryption Standards, cipher, multi processor.

[1]. Bin Liu and Bevan M. Baas "Parallel AES Encryption Engines for Many-Core Processor Arrays" IEEE Transactions on computer, VOL. 62, NO. 3, MARCH 2013.
[2]. A. Still maker, "Exploration of Technology Scaling of CMOS Circuits from 180 nm to 22 nm Using PTM Models in HSPICE, "Technical report, UC Davis, June 2011.
[3]. J. Granado-Criado, M. Vega-Rodriguez, J. Sanchez-Perez, and J. Gomez-Pulido, "A New Methodology to Implement the AES Algorithm Using Partial and Dynamic Reconfiguration," Integration, the VLSI J., vol. 43, no. 1, pp. 72-80, 2010.
[4]. S. Gueron, "Intel Advanced Encryption Standard (AES) Instructions Set," Jan. 2010.
[5]. Z. Yu and B.M. Baas, "A Low-Area Multi-Link Interconnect Architecture for GALS Chip Multiprocessors," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 18, no. 5, pp. 750-762, May 2010.
[6]. M. Butler, "AMD Bulldozer Core—A New Approach to Multithreaded Compute Performance for Maximum Efficiency and Throughput," Proc. IEEE Hot Chips Symp High-Performance Chips (Hot Chips '10), Aug. 2010.

ABSTRACT: An improved design of CMOS dynamic latch comparator with dual input dual output with a simple design of three stages is represented. The basic disadvantages of latch type comparators are overcome by producing an edge triggered comparison. The circuit is designed for a resolution of 300nV and the power consumption is reduced to 450uW. It is designed for 1.8V DC supply voltage and 1 MHz clock frequency for PVT variations. The simulation of the comparator is done in Cadence® Virtuoso Analog Design Environment using 180nm technology. The error quotient is reduced less than 5% by adding a buffer stage. The delay is brought down to 5nS. The active area appreciably is reduced. Layout of the proposed comparator has been simulated in Cadence® Virtuoso Layout XL Design Environment. DRC and LVS have been verified.

[1]. Design of double tail dynamic comparator through analysis of low power consumption of conventional dynamic comparator M.Dinesh kumar, S.Indira PG Scholar, Department of Electronics and Communication Engineering, K.S.Rangasamy College of Technology, Tiruchengode
[2]. High Speed and Low Power Dynamic Latched Comparator for PTL Circuit Applications N. Naga Sudha, V. Narasimha Nayak, Suneel Mudunuru,M. Nagesh Babu,B.K.V Prasad, M. Jyothi,. Tech students, Department of ECE, K L University Vijayawada, INDIA
[3]. Design and Simulation of a High Speed CMOS Comparator Smriti Shubhanand*, Dr. H.P. Shukla,and A.G. Rao Electronics Design and Technology,National Institute of Electronics and Information Technology,MMM Engineering College Campus, Gorakhpur–273 010 (UP), India
[4]. Special Topics in High-Speed Links Circuits and SystemsSpring 2010 RX Comparator Circuits Sam Palermo Analog & Mixed-Signal Center Texas A&M University
[5]. Design of A Novel High Speed Dynamic Comparator with Low Power Dissipation for High Speed ADCsSougata Ghosh,Samraat Sharma Department of Electronics and Communication Engineering Assistant Professor,IFTM University, MoradabadUttarpradesh-244102

ABSTRACT: This paper anticipated the design of a novel Vedic Multiplier using the techniques of Ancient Indian Vedic Mathematics that have been modified to improve performance. A high speed processor depends greatly on the multiplier as it is one of the key hardware blocks in most digital signal processing system as well as in general processors. Currently the speed of the multipliers is limited by the speed of the adders used for partial product addition. In this paper, we proposed an 8-bit multiplier using the new methodology of Vedic Mathematics called as Urdhva-Tiryagbhyam sutra which is used for generating the partial products. The partial product addition in Vedic multiplier is realized using carry-skip technique. This paper depicts the design of an efficient 8×8 binary arithmetic multiplier by using Vedic Mathematics. From various multiplication techniques, Urdhva-Tiryagbhyam sutra is being implemented because this sutra is applicable to all cases of algorithms for N×N bit numbers and the minimum delay is obtained. A 4×4 Vedic Multiplier is designed using 9 –full adder and a special 4-bit adder which is having reduced delay. Then 8-bit multiplier is designed using four 4-bit multiplier and 3-ripple carry adder. Then 8×8 Vedic Multiplier is coded in VHDL, synthesized and simulated using Xilinx ISE8.2 Software. Finally the objective of this paper lies in design of an efficient vedic multiplier using Urdhva–Tiryakbhyam Sutra in VHDL Environment.

Index Terms- Vedic Mathematics, Vedic Multiplier, Urdhva Tiryagbhyam, Digital Signal Processing, VLSI Signal Processing,VHDL,

[1]. AmritaNanda,"Design and Implementation of Urdhva-Tiryakbhyam Based Fast 8×8 Vedic Binary Multiplier"IJERT, ISSN: 2278-0181,Vol. 3 Issue 3, March - 2014
[2]. Poornima M, Shivaraj Kumar Patil, Shivukumar, ShridharKP,Sanjay H, "Implementation of Multiplier Using Vedic Algorithm", JITEE, ISSN:-2278-3075, Volume-2, Issue-6,May-2013.
[3]. Premananda B.S, Samarth S. Pai, Shashank B, ShashankS.Bhat, "Design and Implementation of 8-bit Vedic Multiplier", IJAREEIE, Vol.2, Issue 12, ISSN: 2320-3765, Dec-2013.
[4]. Anju& V.K. Agrawal,"FPGA Implementation of Low Power and High Speed Vedic Multiplier using Vedic Mathematics", IOSR-JVSP , e-ISSN: 2319 – 4200 ,2, Issue 5 (May. – Jun. 2013), PP 51-57
[5]. Booth, A.D., "A signed binary multiplication technique," Quarterly Journal of Mechanics and Applied Mathematics, vol. 4, pt. 2, pp. 236– 240, 1951
[6]. Jagadguru,Swami Sri Bharath, KrsnaTirathji, "Vedic Mathematics or Sixteen Simple Sutras From The Vedas", MotilalBanarsidas, Varanasi(India),1986

ABSTRACT: This paper presents effects on MOS transistor performance due to scaling of its dimensions. Scaling theory deals with the change in the device characteristics with the decrease in the dimensions of a MOS transistor. MOS transistors are continuously scaled down due to the desire for high density and high functionality VLSI chips. The driving forces behind these developments are increasing the demand for portable systems requiring high throughput and high integration capacity. Effects of scaling on the performance characteristics of a MOS device are analyzed in this paper.

Keywords: Scaling, constant field scaling, constant voltage scaling, threshold voltage, scaling factor.

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ABSTRACT: In this paper, a multiplexer based 1 bit full adder cell using 10 transistors is reported ( MBFA-10T). In addition to higher speed , low power and reduced transition activity, this design has no direct power supply connections, results in reduced consumption of short circuit current. The design was implemented using Cadence Virtuoso tools in 180-nm CMOS technology. Performance parameters like layout area, power delay product(PDP), transistor count, average power and delay were compared with the existing logic design styles like static CMOS logic, pass transistor logic( TFA-16T, 14 T) , transmission gate logic and so on. The intensive simulation shows improved operation speeds and power savings compare to the conventional design styles. For 1.8-V supply at 180-nm CMOS technology, the average power consumption (3.9230μW) ,delay (196.8ps) ,the power delay product (PDP) (0.772fJ) and lay out area(175.79 μm2) was found to be extremely low, when compared with other potential design styles.

Keywords: Multiplexer, full adder ,Very large scale integration( VLSI), low power, Complementary metal oxide semiconductor(CMOS).

[1]. Mariano Aguirre-Hernandez and Monico Linares-Aranda, "CMOS Full Adders for Energy Efficient Arithmetic Applications," IEEE Tran. on VLSI Systems, Vol 19, No. 4, pp. 718-721, April 2011.
[2]. N. Weste and K. Eshraghian, Principles of CMOS VLSI Design, A SystemPerspective. Reading, MA: Addison-Wesley.
[3]. Y. Jiang, Al-Sheraidah. A, Y. Wang, Sha. E, and J. G. Chung, "A novel multiplexer-based low-power full adder," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 51, pp.345–348, July 2004.
[4]. S. Goel, A. Kumar, and M. Bayoumi, "Design of robust, energy-efficient full adders for deep-submicrometer design using hybrid-CMOS logic style," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 14,no. 12, pp. 1309–1320, Dec. 2006.
[5]. C. Chang, J. Gu, and M. Zhang, "A review of 0.18-umfull adder performances for tree structured arithmetic circuits," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 6, pp. 686–695, Jun. 2005.

ABSTRACT: The project is mainly focusing on multiple error detection and correction. Digital filters are widely used in signal processing and communication n systems. In some cases, the reliability of those systems is critical and fault tolerant implementations are needed. So that, the idea is generalized to show that parallel FIR filters can be protected using error correction codes. Triple Modular Redundancy (TMR) is the traditional mitigation techniques for Field-Programmable Gate Arrays (FPGAs) subject to Single-Event Upsets (SEUs) in high radiation environment. To overcome the problem, in our project we propose RFFF (Reduced Faultless FIR Filter) is a technique combined with TMR used to multiple errors are detected and corrected. TMR increases the parameters like area, power and delay. In RFFF, multiple errors are corrected and the comparison of parameters like area, power and delay of existing and the proposed technique is done.

Keywords: Error correction codes (ECCs), filters, Reduced Faultless FIR Filter (RFFF), Triple Modular Redundancy (TMR)..

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[3]. B. Shim and N. Shanbhag, "Energy-efficient soft error-tolerant digital signal processing," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 14, no. 4, pp. 336–348, Apr. 2006.
[4]. T. Hitana and A. K. Deb, "Bridging concurrent and non-concurrent error detection in FIR filters," in Proc. Norchip Conf., 2004, pp. 75–78.
[5]. Y.-H. Huang, "High-efficiency soft-error-tolerant digital signal processing using fine-grain subword-detection processing," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 2, pp. 291–304,Feb. 2010.
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