iosr-JVSP   Volume-5 ~ Issue-3 ~ May-June 2015

ABSTRACT: CRC is playing a main role in the networking environment to detect the errors. With challenging the speed of transmitting data to synchronize with speed, it is essential to increase speed of CRC generation. Most electronics engineers are familiar with the cyclic redundancy check (CRC).In the era of high speed data transmission, there requires a lot of accuracy for the message to be sent correctly to the receiver. And to check whether the message is correctly sent or not, an error detection technique called "CRC generation and check" is used. This technique informs the sender if any error is occurred. We know that it is widely used in communication protocols to detect bit errors and that it is essentially a remainder of the modulo-2long division operation.

[1]. Hitesh H. Mathukiya, "A Novel Approach for parallel CRC generation for high speed application, "International conference on communication system and network technologies, no. 978-0-7695-4692-6/12-2012 IEEE.
[2]. Yan Sun; Min Sik Kim. "A Pipelined CRC Calculation Using Lookup Tables," Consumer Communications and Networking Conference (CCNC), 2010 7th IEEE , vol., no., pp.1-2, 9-12 Jan.2010
[3]. G. Campobello, G. Patane, and M. Russo, "Parallel CRC realization," IEEE Transactions on Computers, Oct. 2003.
[4]. Weidong Lu and Stephan Wong, "A Fast CRC Update Implementation", IEEE Workshop on High Performance Switching and Routing, Oct. 2003.
[5]. Tom´aˇs Z´avodn´ık, Luk´aˇs Kekely, Viktor Puˇs, "CRC Based Hashing in FPGA Using DSP Blocks" at 978-1-4799-4558-0/14/$31.00 ©2014 IEEE

ABSTRACT: Biometric system is one of the mainly adopted security system in the present world. This paper presents a face recognition biometric system using Dual tree complex wavelet transform(DTCWT). The technique is applied on Combined database for matching purpose. The reults are obtained in the terms of FAR, FRR, EER and TSR. Keywords - DTCWT, Combined database

[1] Ali Cheraghain, Brendan Klare, and Unsang Park, "Face Recognition: some challenges in Forensics," IEEE International Conference on Automatic Face and Gesture Recognition, pp. 726-733, May 2011

[2] Chengliang Wang, Hu, Aggarwal .J. K, "Fusing Face Recognition from Multiple Cameras," IEEE International Conference on Applications of computer vision, pp.1-7, Feb. 2010

[3] GayathriMahalingam, Xiaoou Tang, "Face Photo Sketch Synthesis And Recognition," IEEE International Conference on Pattern Analysis and Machine Intelligence, pp. 1955-67, Sept. 2008

[4] Zhifeng Li, Myung Jin Chung, "Pose-Robust Face Recognition Based On Texture Mapping,"IEEE International Conference on Machine Learning and Cybernerics, pp. 46-51, Aug. 2008

[5] Muhammad Ashraf, ZubairSajid, Muhammad Sarim and Abdul BasitShaikh, "Face Recognition Using Weighted Distance Transform" Proceedings of 2013 10th International Bhurban Conference on Applied Sciences & Technology (IBCAST)

[6] S.Anith, D.Vaithiyanathan, R.Seshasayanan, "Face Recognition System Based on Feature Extraction

ABSTRACT: Still Images and video clips are common formats for storing and sharing information in different fields. Information content in such multimedia formats is huge and requires compression. Compression is done to reduce redundant information content while maintaining good perceptual video or Image quality for Human Visual Systems (HVS) and involves signal transformation together with other operations. While MPEG-X and H.26X deploy DCT (Discreet Cosine Transform), Discreet Wavelet Transforms (DWTs) are common in different multimedia CODECs such as MJPEG2000, MJPEG-XR and MJPEG-LS. DWT like all other transformations requires intensive computation and consume more power. To mitigate the trade-off between computation duration, bulkiness of subsystems and power consumption, Software-Hardware co-design approach is used. In this approach, Hardware modules called hardware accelerators are reserved for intensive functions and are called by the main program as a subroutine, thus a good flexible design approach is required for such hardware circuit modules. In this paper, we revisit the fundamentals of Haar DWT. We exploit its flexibility and simplicity to design a relaxed Hardware module that can be used to process a 16x16 spatial micro block from an Image or a video frame without multiplication because multiplications takes longer and hence more power consumption. The Module is Implemented on FPGA

Keywords– Discreet Wavelet Transform, Multimedia Compression, Hardware Realization, FPGA.

[Chih-Hsien Hsia, et al, Memory-efficient architecture of 2-D lifting-based discrete wavelet transform, Journal of the Chinese Institute of Engineers, Published online: 28 Jun 2011.
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[4]. Jason Spielfogel, Why we like MJPEG compression,http://www.securityinfowatch.com/article/10561410/why-we-like-mjpeg-compression[Accessed on 4th may, 2015].
[5]. Dragomir El Mezeni et el , JPEG-XR encoder implementation on a heterogeneous multiprocessor system, 5th European Conference on Circuits and Systems for Communications (ECCSC'10), November 23–25, 2010, Belgrade, Serbia

ABSTRACT: In the absence of an opportunity to physically interaction with products in the online environment, online information plays a critical role in enabling e-Commerce consumers purchase decisions. Thus, it is critical to understand what leads to consumer satisfaction with online information quality. This paper investigates how the quality of certain attributes of e-commerce systems ― such as information quality, system quality, and service quality ― can be leveraged to enhance business benefits as indicated by customer commitment and customer retention. This study argues that relationship quality, a concept encapsulating the ideas of both trust and satisfaction, is crucial for transferring attributes of e-commerce systems into business benefits.

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ABSTRACT: The explosive growth of the semiconductor industry over the past decade has been driven by the rapid scaling of complementary metal-oxide-semiconductor (CMOS) technology. Interconnects still is the major area which continues to gain attention of designers as they play crucial role in Power, Delay and area of any chip. With use of Multiple-valued logic it is possible to reduce the number of bits used to represent information in the circuit, so can be used to reduce the impact of interconnections.

[1]. Debasis Mukherjee, Hemanta Kr. Mondal and B.V.R. Reddy "Static Noise Margin Analysis of SRAM Cell for High Speed Application", IJCSI International Journal of Computer Science Issues, Vol. 7, Issue 5, September 2010
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[2]. Sung-Mo Kang , Yusuf Lablebici . CMOS Digital Integrated Circuit : Analysis and Design.( Third Edition Mc Graw Hill Publication. )
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[3]. Chapter 6 , Sung-Mo Kang , Yusuf Lablebici . CMOS Digital Integrated Circuit : Analysis and Design.( Third Edition Mc Graw Hill Publication. ).

ABSTRACT: Now a days as far as technology going to advances still some problem in VLSI interconnect. Cu interconnect is batter As compared with gold, silver Even though cu interconnect also major drawback because billion of transistor were integrating single chip. So Interconnect Delay is major problem. In this paper compares the Cu interconnect with CNT interconnect and performances parameter like power delay and power delay product were taken at Intermediate and global level with Different technology for analysis. from the Simulation, it found that CNT based interconnect is suited for high performances application .the simulation has done using T_Spices Keywords: Cu, CNT, T_SPICE, Power, Delay

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ABSTRACT: This paper focused on impact of self-directed learning strategy as a tool for promoting critical thinking and problem solving skills among Social Studies students. The discipline (Social Studies) in Nigeria for long had been criticized for not quite preparing students for effective living in the society as result of inappropriate utilization of teaching and learning strategies in its classroom interaction. This is because the classroom activities of the discipline focused mainly on activities which the students acquire facts, rules, and action sequences. Majority of the Social Studies lessons require outcomes only at the lower levels of cognition: knowledge, comprehension and application.

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ABSTRACT: Microcontrollers and FPGAs are the soul of Digital Circuit Design. Microcontrollers high speed ,low power dissipation and reduced prices make them an obvious choice on one hand and on the other hand, The reconfigurable power, high speed and high density have made FPGA based systems an alternative choice.These both technologies are unmatched in their own domains but it is valuable to identify the different design patterns which can provide canonical solutions to the common problems based on FPGA integrated with Microcontrollers and we have taken a small step towards it by demonstrating the integration of both the technology with the help of an application in which a data sharing architecture (FPGA based) which we have designed earlier integrated with AVR AT90S8515 microcontroller.

Keywords: FPGA Master/ Slave Processor, PCI Reconfigurable Computing,Microcontroller

[1]. Bhavya Alankar and BK Kanaujia,A Compact Priority based architecture designed and Simulated for Data Sharing based On Reconfigurable Computing,Journal of Computing,Volume 4, Issue 4, April 2012.
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[4]. Banerjee,T.P,konar,chaudhary High-speed communication sys-tem developed using FPGA based CAM implementation published in ICETET-2009

ABSTRACT: This paper presents a multiprecision (MP) dynamic and partially reconfigurable fir filter that incorporates variable precision, parallel processing (PP) multiplier, razor-based error detection, dynamic frequency scaling and dedicated operands scheduling to give optimum performance for a variety of operating conditions. Each of the building blocks of the proposed architecture can either work as independent smaller-precision systems or work in parallel to execute higher-precision system. Our aim is to realize a less-delay; area-efficient reconfigurable digital signal processing design that is implemented using Xilinx Synthesis Tool on Virtex5 FPGA kit.

[1]. S.-R. Kuang and J.-P. Wang, "Design of power-efficient configurable booth multiplier,"IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 3, pp. 568–580, Mar. 2010.
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ABSTRACT: In this paper the built in self test for analog to digital converter of programmable system on chip is implemented. The new approach for finding out static errors in ADC is based on time. This approach uses ramp signal and determines time difference between two successive samples, which in turn leads to finding out the static error like DNL, INL of the ADC. The proposed work uses PSoC devices which enable us to design a complete mixed signal system with few off chip components To test static parameter of ADC on chip components are used. Ramp signal is generated by using on chip IDAC of PSoC. The BIST circuit implemented here calculate DNL, INL based on timing i.e. a new approach to calculate DNL, INL is implemented and verified.

Keywords: BIST, Mixed Signal, ADC, PSoC

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[2]. Zbigniew Czaja Gdansk, "A fault diagnosis method of analog electronic circuits for mixed-signal systems controlled by microcontrollers",IMTC 2006 – Instrumentation and Measurement Technology Conference Sorrento, Italy 24-27 April 2006.
[3]. Jiun-Lang Huang, Chee-Kian Ong, and Kwang-Ting Cheng, "A BIST scheme for on-chip ADC and DAC testing" In Proceedings of the conference on Design, automation and test in Europe (DATE '00). ACM, New York, NY, USA, 216-220.
[4]. Wibbenmeyer, J.; Chen, C.-I.H., "Built-In Self-Test for Low-Voltage High-Speed Analog-to-Digital Converters," Instrumentation and Measurement, IEEE Transactions on , vol.56, no.6, pp.2748,2756, Dec. 2007.
[5]. Hanqing Xing; Hanjun Jiang; Degang Chen; Geiger, R.L., "High-Resolution ADC Linearity Testing Using a Fully Digital-Compatible BIST Strategy," Instrumentation and Measurement, IEEE Transactions on , vol.58, no.8, pp.2697,2705, Aug. 2009.