iosr-JVSP   Volume-6 ~ Issue-4 ~ Jul-Aug 2016

ABSTRACT: The LDPC codes are commonly used , the most promising coding technique to achieve the Shannon capacity.In spite of their effectiveness, encoding, and decoding, the LDPC codes are complex to design, due to their size and structure of the codes. This paper presents a fully parallel architecture of low-density-parity-check (LDPC) decoder using Min-sum decoding algorithm for IEEE 802.11n Standard. The proposed architecture utilizes features of Quasi-Cyclic LDPC codes to reduce interconnection complexity The LDPC decoder hardware implementation works at 69.06 MHz and it can process 82.24 Mbps for 648 block length and 1/2 code rate, on a Xilinx Virtex -5 FPGA,. The results show good speed with lower area as compared to state-of-the-art of proposed circuit.

Keywords: LDPC codes, Quasi-cyclic low density parity check (QC-LDPC), Min-Sum algorithm, IEEE802.11n

[1]. R. G. Gallager, Low-density parity check codes, IRE Transaction Info. Theory,8,1962,21–28.
[2]. D.J.C. MacKay and R.M. Neal, Near shannon limit performance of low density parity check codes. Electronics Letters, 32(18), 1996,1645-1646.
[3]. Qian Xie, Qian He, Xiao Peng, Ying Cui, Zhixiang Chen, Dajiang Zhou, Satoshi Goto, A High Parallel Macro Block Level Layered LDPC Decoding Architecture based on Dedicated Matrix Reordering:Proc, IEEE Workshop on Signal Processing Systems (SiPS- 2011), Beirut, Lebanon ,2011, 122-127.
[4]. Ying Cui, Xiao Peng, Zhixiang Chen, Xiongxin Zhao, Yichao Lu, Dajiang Zhou and Satoshi Goto Ultra Low Power QC-LDPC Decoder with High Parallelism:Proc.IEEE International SOC Conference (SOCC2011) Taipei, Taiwan,2011,142-145.
[5]. Zhixiang Chen, Xiao Peng, Xiongxin Zhao, Qian Xie, Leona Okamura, Dajiang Zhou and Satoshi Goto, A Macro-Layer Level Fully Parallel Layered LDPC Decoder SoC for IEEE 802.15.3c Application:Proc. IEEE InternationalSymposium on VLSI Design, Automation and Test (VSLI-DAT 2011), Hsinchu,Taiwan, 2011,1-4.

ABSTRACT: Arithmetic and Logic Unit (ALU) is the most crucial and core component of central processing unit as well as of number of embedded systems and microprocessors. ALU consists of many computational units like adders, multipliers, logical units etc. Vedic Mathematics concepts are proposed here for designing the computational units of an 8-bit ALU. Here, a high-speed 8×8 bit multiplier is proposed which is based on the Vedic multiplier mechanism. A divider based on vedic mathematics is also proposed here. The proposed Vedic mathematics based ALU is designed using high level hardware description language – Verilog, followed by synthesization using EDA tool, Xilinx ISE 14.1. Finally, the synthesized circuit has been implemented on Xilinx Spartan-6 Field Programmable Gate Array (FPGA) device......

Keywords: ALU, FPGA, Vedic mathematics, Verilog – HDL, Xilinx ISE 14.1

[1] Garima Rawat, Khyati Rathore, Siddharth Goyal, Shefali Kala and Poornima Mittal, "Design and Analysis of ALU: Vedic
Mathematics Approach", Proc of International Conference on Computing, Communication and Automation (ICCCA2015), IEEE,
15-16 May 2015, pp 1372 – 1376.
[2] Rahul Nimje, Sharda Mungale, "Design of arithmetic unit for high speed performance using vedic mathematics, International
Journal of Engineering Research and Applications, April 2014, pp 26 – 31.
[3] Abhishek Gupta, Utsav Malviya, Vinod Kapse, "A novel approach to design high speed arithmetic logic unit based on ancient
vedic multiplication technique", International Journal of Modern Engineering Research, Vol. 2, no. 4, July, 2012, pp 2695 – 2698.
[4] Suchita Kamble, N. N. Mhala, "VHDL implementation of 8- bit ALU", IOSR Journal of Electronics and Communication
Engineering, Vol. 1, no. 1, May 2012, pp 07 – 11.
[5] S.P.Pohokar, R.S.Sisal, K.M.Gaikwad, M.M.Patil, Rushikesh Borse, "Design and Implementation of 16 x 16 Multiplier Using
Vedic Mathematics", Proc of International Conference on Industrial Instrumentation and Control (ICIC), IEEE, 28-30 May 2015, pp
1174 – 1177.

ABSTRACT: RAdio Detection And Ranging (RADAR) has been used since 1930's for the detection and estimation of target related information. Earlier Pulse radars were used to determine the target, in which there was time interval between the transmissions of pulses, which in turn induced error in determination of target. To prevent this ambiguity Continuous Wave (CW) radars were used, non modulated CW radar was unable to find velocity of target. So Frequency Modulated Continuous Wave (FMCW) radar is used when we have to find velocity of moving target.......

Keywords: RADAR, FMCW, FFT, FPGA, target, Range, Velocity

[1]. M. I. Skolnik, Introduction to radar systems, 3rd ed. Mc- Graw-Hill Ltd., 2001.
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ABSTRACT: In this paper, using hamming code technique the parallel FIR filters is designed and implemented. In DSP systems the digital filters are very important and in present days the complex circuits are designed and reliability is an important criteria. Fault tolerant parallel FIR filters are to be implemented for reliability purposes. Using case study the improvements in error correction and circuit cost is determined. By using this hamming code technique, the FIR filter is considered as a bit. By using more filters the area is increased and the delay is reduced to improve performance of the circuit.......

Keywords: Faults, Parallel FIR filters, Hamming codes

[1]. S.Ranjani, Multi fault detection and correction using error correction codes and parsevel checks, IEEE trans.VLSI systems vol .5(4), march 2016.
[2]. Arun.k.Somani, Soft Error Mitigation Schemes For High Performance & Aggressive Designs, 344 publications, 10 march 2016.
[3]. T.Saranya, Highly reliable parallel filter design based on reduced precision error correction codes, IEEE trans. VLSI syst.,vol.5(1),ver 3, feb 2015,45-48.
[4]. R.Mamatha Rani, Design of low power efficient FIR digital filter, IEEE trans. VLSI syst., vol 4(10), October 2014.
[5]. Dhiraj.k.pradhan, Fault tolerant single error correction encoders, IEEE transactions,springer,30 march 2011.

ABSTRACT: This paper presents parametric area estimation model for implementation using FPGA's from the Xilinx Spartan 3E family. Accurate estimates of the FPGA resources required provides the system designer important feedback on area which is valuable even during early design iterations. Detailed model for accurately estimating the number of LUT's, block RAMs and 18X18 multipliers for benchmark circuits like FFT8,DCT8 etc.. have been developed. In all cases model coefficients have been derived by using curve fitting analysis. Estimates are conservative, and accurate to within 12% of the post-mapping implementation report. In this paper ,we explain how block resource information is characterized in a MATLAB function. Area estimation in terms of LUT's is with an average error of 6.37% for Spartan 3E........

Keywords: Area Estimation, Field Programmable gate array (FPGA), HW/SW Partitioning, High-level synthesis.

[1]. Shi C., Hwang, J., McMillan, S., Root, A., and Singh, V.,"A System Level Resource Estimation Tool for FPGAs",International Conference on Field Programmable Logic andApplications (FPL),LHCS 3203,pp.423-433,2004.
[2]. RoelMeeuws, "A Quantitative model for Hardware/Software partitioning," MSc thesis, Delft University of Technology, Delft,Netherland,Tech.Rep.RCOSY DES.6392,pp 735-739,2007.
[3]. V. Srinivasan, S. Govindarajan, and R. Vemuri, "Fine-grained and coarse-grained behavioral partitioning with effective utilization of memory and design space exploration for multi-FPGA architectures," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 9, no. 1, pp. 140–158, 2001.
[4]. F. Vahid and D. D. Gajski, "Incremental hardware estimation during hardware/software functional partitioning," in Readings in hardware/software co-design, G. De Micheli, R. Ernest, and W.Wolf (eds.), Morgan Kaufmann, pp. 516–521, 2002.
[5]. L. Yan, T. Srikanthan, and N. Gang, "Area and Delay Estimation for FPGA Implementation of Coarse-Grained Reconfigurable Architectures," LCTES, Ottawa, Ontario, Canada,pp.182–188, 2006.

ABSTRACT:Now a day's reversible logic is an attractive research area due to its low power consumption in the field of VLSI design circuit. This paper presents reversible carry skip adder using various reversible logic gates. The classical set of gates such as AND, OR & EX-OR are not reversible. Reversible logic circuits provide low power dissipation as well as zero fan out. In this paper carry skip adder is designed using Modified HNG& Modified FRGgates, thus provided low quantum cost and power dissipation. The comparative result shows that the proposed design is much better in terms of power.

Keywords: Reversible logic, Reversible gates, Quantum cost, Power dissipation

[1]. Landauer.R "Irreversibility and Heat Generation in the Computational Process", IBM Journal of Research and Development, 5, pp. 183-191, 1961.
[2]. Bennett C H "Logical Reversibility of Computation", IBM J.Research and Development, pp. 525-532, November 1973.
[3]. Majid Mohammadi, Mohammad Eshghi, Abbas Bahrololoom,‟‟ Behavioral Model ofV and V+ Gates to Implement the reversible Circuits Using Quantum Gates‟‟, IEEE, 2008.
[4]. D. Michael Miller and Zahra Sasanian,‟‟ Lowering the Quantum Gate Cost of Reversible Circuits‟‟, IEEE, 2010.
[5]. Prashant .R.Yelekar,Prof. Sujata S. Chiwande, "Introduction to Reversible Logic Gates & its Application", 2nd National Conference on Information and Communication Technology (NCICT) 2011.

ABSTRACT: FIR digital filters find immense applications in mobile communications systems such as channel equalization, channelization, matched filtering and pulse shaping, due to their absolute stability and linear phase properties. In this paper it is proposed to design a practical FIR filter using MATLAB tool to obtain the response. After that the filter will be designed and analyzed based on canonical signed digits and compared with the distributed arithmetic algorithm in order to minimize the power consumption and fast implementation of the filter. The design filter will be simulated and synthesized using Xilinx ISE 13.1 software.

Keywords: FIR, CSD, DA, VERILOG HDL

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ABSTRACT: Network attacks that flow through network firewalls or network intrusion detection systems (NIDS) are often identifiable by the patterns of data that they contain. The patterns are normally represented by complex regular expressions which are matched at a very high speed. The regular expressions are built into their equivalent automata, using minimal hardware resources in order to detect variations of these patterns. This paper explains the design, structure, and suitability of a hardware-based automata implementation. The approach is based on an input compression technique that uses Equivalence Classification (EC) technique. The technique is used to drive a novel Nondeterministic............

Keywords: ECDs, ECD-NFA, FPGA, LUTs, Throughput.

[1]. J. Aycock, Computer Viruses and Malware. USA: Springer, 2006.
[2]. P. Piyachon and Y. Luo, "Compact state machines for high performance pattern matching, in Proceedings of the 44th Annual Conference on Design Automation - DAC '07, 2007, pp. 493-496.
[3]. M. Roesch, Snort - lightweight intrusion detection for networks, in Proceedings of the 13th USENIX Conference on System Administration, LISA'99, 1999, pp. 229-238.
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ABSTRACT: This paper presents design and detailed FFT analysis for CMOS sense amplifiers for dynamic and static memories. Sense amplifiers in association with semiconductor memories are the key elements in defining the overall performance of CMOS memories. The presented design is implemented using C5 process technology using BSIM-4 Spice models for both open book and closed book architectures. The design includes circuit and operation descriptions, transient signal analysis, FFT analysis, also evaluation of magnitude, phase, and group delay is done at range frequency range from 100 MHz to few GHz. The paper also presents a physical design and interfacing logic for interfacing DRAM Memory arrays to Sense amplifiers and operating point analysis for the same.

Keywords: Sense Amplifiers, DRAM, FFT, CMOS Memories, Sense amplifier interfacing

[1] Jain, Ginni, et al. "Slew rate and delay optimization of sense amplifier using tradeoff between supply voltage and threshold." Electrical Insulation Conference (EIC), 2015 IEEE. IEEE, 2015.
[2] Haraszti, Tegze P. CMOS memory circuits. Springer Science & Business Media, 2007.
[3] Ghosh, Swaroop, Mesut Meterelliyoz, Faith Hamzaoglu, Yih Wang, and Kevin X. Zhang. "DRAM with pulse sense amp." April 21, 2015.
[4] Zhang, Hua, and Ling Lu. "A Low-Voltage Sense Amplifier for Embedded Flash Memories." Circuits and Systems II: Express Briefs, IEEE Transactions on 62.3 (2015): 236-240."
[5] Wu, Wenqing, Venkatasubramanian Narayanan, and Kendrick Hoy Leong Yuen. "Sense amplifiers employing control circuitry for decoupling resistive memory sense inputs during state sensing to prevent current back injection, and related methods and systems." U.S. Patent No. 9,087,579. 21 Jul. 2015.

ABSTRACT: The term very large scale integration reflects the capabilities of the semiconductor industry to fabricate a complex electronic circuit consisting of thousands of components on a single chip. Over the last two decades, low-power design has become a concern in digital VLSI design, especially for portable and high performance systems. A single silicon LSI chip may contain tens of thousands of transistors. Scaling of technology node increases power-density more than expected. CMOS technology beyond 50nm node represents a real challenge. Low cost always continues to drive higher levels of integration, whereas low cost technological breakthroughs to keep power under control are getting very scarce............

Keywords: CMOS, DGMOSFET, FINFET, Ion/Ioff, low power, power dissipation, leakage current, Schmitt trigger

[1] Pawan Sharma ; Dept. of ECE, ITM, Gwalior, India ; Saurabh Khandelwal ; Shyam Akashe''design and optimization of Finfet based schmitt trigger"2015 ,IEEE Fifth International Conference on Advanced Computing & Communication Technologies
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ABSTRACT: Attacks on various computer networks are usually in form of patterns of attack. The patterns are recognizable mostly based on the data that their respective packet payload contains. Attack patterns usually occur as strings or regular expression patterns, which are then converted into their equivalent automata. To create an efficient automata, there is a need for the automata design to consume less memory resources per each state of the automata. This is important whenever the design attempts to detect variations of these patterns. This paper explains the design, structure, and suitability of the hardware memory architecture for a Field Programmable Gate Array (FPGA) based automata design.............

Keywords: ECDs, ECD-NFA, FPGA, LUTs, throughput.

[1]. J. Aycock, Computer Virus and Malware, N.Y, USA: Springer, 2006.
[2]. Snort, "Snort IDS/Rules," [Online]. Available: http://www.snort.org/. [Accessed 18 July 2013].
[3]. Y. E. Yang, W. Jiang and V. K. Prasanna, "Compact Architecture for High-Throughput Regular Expression Matching on FPGA," in Proceedings of the 4th ACM/IEEE Symposium onArchitectures of Networking and Communications Systems-ANCS'08, San Jose, CA, USA, 2008.
[4]. C. Clark and D. Schimmel, "Scalable Pattern Matching for High Speed Networks," in 12th Annual IEEE Symposium on Field-Programmable Custom Computing Matchines, Washington DC, USA, 2004.
[5]. B. Modi and G. Tripp, "A Highly Compressible Regular Expression Matching Circuit for Network Intrusion Detection Systems: An ECD-NFA Approach," Journal of VLSI and Signal Processing (IOSR-JVSP), no. (Ackowledged and under Review), 2016.

ABSTRACT: The continuous scaling down of feature size in Silicon technology has resulted in several technological and fundamental hindrances. The researchers started to look for new nanoscale devices those can replace CMOS transistors in digital circuits. The nanowire transistor, FinFET, Carbon Nanotube field effect transistor (CNFET), tunnel field effect transistor (TFET), and single electron transistor (SET) emerged as potential future replacement for CMOS transistors in digital circuits. CNFETs are being considered to be most promising device because of its novel properties like high current carrying capability (~ 1010 A/cm2), excellent carrier mobility, scalability, high reliability for elevated temperature operation, and negligible leakage current.............

Keywords: CMOS, CNT, CNFET, FinFET, NAND, NOR, SWCNT, MWCNT.

[1] International Technology Roadmap for Semiconductors (ITRS) reports, http://www.itrs.net/Links/2005ITRS/Home2005.html
[2] Kim, Yong-Bin. "Integrated Circuit Design Based on Carbon Nanotube Field Effect Transistor‖, IEEE Journal of Transactions on Electrical and Electronic Materials, Vol. 12, No. 5, pp. 175-188, 2011.
[3] S. K. Sinha, S Chaudhury, "Advantage of CNTFET characteristics over MOSFET to reduce leakage power‖, in proceedings of IEEE second International Conference on Devices Circuits and Systems (ICDCS), pp 1-5, 2014.
[4] C. S. Lee, E. Pop, A. D. Franklin, W. Haensch and H.S. P. Wong, ―A Compact Virtual Source Model for Carbon Nanotube FETs in the Sub-10-nm Regime—Part I: Intrinsic Element‖, IEEE transactions on Electron Devices, vol. 62, no. 9, pp. 3061-3069, September 2015.
[5] S. Lin, Y. B. Kim and F. Lombardi, "Design of a Ternary Memory Cell Using CNTFETs‖, IEEE Transactions on Nanotechnology, vol. 11, no. 5, pp. 1019-1025, Sept. 2012.