iosr-JVSP   Volume-1 ~ Issue-3

ABSTRACT:The Operational Transconductance amplifiers are significant building blocks for different analog circuits and systems which were previously implemented by using OPAMP. Recently, research is going on for implementing OTA circuits which will be highly linear, consumes lesser power and operate at lower supply voltage. Previous OTAs seldom worked over 200MHz whereas, the higher frequency OTA can be used as basic building block in several RF as well as microwave applications. The performance analysis of conventional OTA techniques and suggesting the topology, using advanced process technology that can break the previous frequency barrier is a key objective of this paper. Study and Analysis of different OTA topologies has been done. The appropriate topology is suggested which has a perfect balance between complexity and performance. The research includes analysis and comparison of OTA topologies from the point of view of effect of technology scaling on various performance parameters such as transconductance, supply voltage, Power consumption, dc gain, Frequency range, etc.
Keywords:CMOS, Frequency range, Operational Transconductance Amplifier (OTA), Operational amplifier (OPAMP), Transconductance.

[1] You Zheng and Carlos E. Saavedra, "Feed forward-Regulated Cascode OTA for Gigahertz Applications", IEEE Transactions on
Circuits and Systems, 2008
[2] Anil Kavala, Kondekar P. N, and Yang Sun, "A low voltage, low power linear pseudo Differential OTA for ultra-high frequency
applications", IEEE, International workshop on Antenna Technology, 2009.
[3] M.Siripruchyanun & W.Jaikla, "Current controlled current conveyor Transconductance Amplifier (CCTA):a building block for
analog signal processing", Electrical Eng (2008) 90:443–453 Springer-Verilog, 2008.
[4] Berg, Y., "Novel ultra low voltage Transconductance amplifier", Proceedings of 2010 IEEE International Symposium on Circuits
and Systems, 2010.
[5] N. Raj, R. K. Sharma, A. Jasuja and R. Garg, "A Low Power OTA for Biomedical Applications", Cyber Journal: A multi
disciplinary Journal in science & technology, 2010.
[6] Sheng-Wen Pan1, Chiung-Cheng Chuang2, Chung-Huang Yang3, Yu-Sheng Lai., "A novel OTA with dual bulk-driven input
stage", IEEE International Symposium on Circuits and Systems, 2009.
[7] Y.L. Li, K.F. Han, X. Tan, N. Yan and H. Min, "Transconductance enhancement method for Operational Transconductance
amplifiers", Electronics Letters (International journal on rapid Communication by IET, UK), 2010.
[8] Tsung-Hsien Lin, Chin-Kung Wu, and Ming-Chung Tsai, "A 0.8-V 0.25-mW Current-Mirror OTA With 160-MHz GBW in 0.18-
_m CMOS", IEEE Transactions on Circuits And Systems II:Vol. 54, No. 2, 2007.
[9] You Zheng, and Carlos E. Saavedra, "Feed forward Regulated Cascode OTA for Microwave Applications", IEEE Transactions on
Circuits and Systems, Vol.55, 2008.
[10] Tsung-Hsien Lin, Member, IEEE, Chin-Kung Wu, and Ming-Chung Tsai, "A 0.8-V 0.25-mW Current-Mirror OTA With 160-
MHz GBW in 0.18 μm CMOS", IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 54,
NO. 2, FEBRUARY 2007.

ABSTRACT:It is well known that multipliers consume most of the power in DSP computations. Hence, it is very important for modern DSP systems to develop low-power multipliers to reduce the power dissipation.. In this paper, we presents low power Column bypass multiplier design methodology that inserts more number of zeros in the multiplicand thereby reducing the number of switching activities as well as power consumption. The switching activity of the component used in the design depends on the input bit coefficient. This means if the input bit coefficient is zero, corresponding row or column of adders need not be activated. If multiplicand contains more zeros, higher power reduction can be achieved. To reduce the switching activity is to shut down the idle part of the circuit, which is not in operating condition. Use of look up table is an added feature to this design. Further low power adder structure reduces the switching activity. Flexibility is another critical requirement that mandates the use of programmable components like FPGAs in such devices..
Keywords: Low Power, Multiplier, Reduced Switching,Column By passing

[1] Oscal T. -C. Chen, Sandy Wang, and Yi-Wen Wu, .Minimization of Switching Activities of Partial Products for Designing Low-Power Multipliers., IEEE Transactions on VLSI Systems, June 2003 vol. 11, no. 3.
[2] Rajendra M. Patrikar, K. Murali, Li Er Ping, .Thermal distribution calculations for block level placement in embedded systems., Microelectronics Reliability 44(2004) 129-134
[3] Hichem Belhadj, Behrooz Zahiri, Albert Tai .Power-sensitive design techniques on FPGA devices., Proceedings of International conference on IC Taipai (2003).
[4] A. Wu, .High performance adder cell for low power pipelined multiplier., in Proc. IEEE Int. Symp. on Circuits and Systems, May 1996 , vol. 4, pp. 57-60.
[5] S. Hong, S. Kim, M.C. Papaefthymiou, and W.E.Stark, .Low power parallel multiplier design for DSP applications through coefficient optimization., in Proc. of Twelfth Annual IEEE Int. ASIC/SOC onf., Sep. 1999, pp. 286-290.
[6] C. R. Baugh and B. A.Wooley, .A two.s complement parallel array multiplication algorithm., IEEE Trans. Comput., Dec. 1973, vol. C-22, pp. 1045-1047.
[7] I. S. Abu-Khater, A. Bellaouar, and M. Elmasry, Circuit techniques for CMOS low-power highperformance multipliers., IEEE J. Solid-State Circuits, Oct. 1996, vol. 31, pp. 1535-1546.
[8] J. Ohban, V.G. Moshnyaga, and K. Inoue, .Multiplier energy reduction through bypassing of partial products,. Asia-Pacific Conf. on Circuits and Systems. 2002.,vol.2, pp. 13-17.

ABSTRACT:A circuit design for a new high speed and Low Power 4-bit Braun Multiplier is presented. The multiplier is implemented by using different power reduction techniques. To design a multiplier it is necessary to design an AND gate and Full Adder circuit using the power reduction techniques is presented. The design uses CMOS digital circuits in order to reduce the power dissipation while maintaining computational throughput. This paper presents an accurate method of simulating the power dissipation, delay and power delay product, using different techniques in 250nm technology with supply voltage is 2.5v. The power dissipation of nearly 41% and delay 26% has been reduced by using modified proposed technique with good voltage swing levels.
Keywords: A low-power 4-bit Braun multiplier, power reduction techniques.

[1]. N. Weste, and K. Eshraghian, "Principles of CMOS VLSI Design", Addison-Weslet Publishing company, 1992.

[2]. J. M. Rabaey, M. Pedram, "Low Power Design Methodologies", Kluwer Academic Publishers, 1996

[3]. Low-Power Domino Logic Multiplier Using Low-Swing Technique A. Rjoub and 0. Koufopavlou 0-7803-5008- 1/98/$10.0001998 IEEE

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ABSTRACT:IThe VLSI placement problem is to place the objects into fixed die such that there are no overlaps among the objects and some cost metric such as wire length and routability is optimized. For this purpose A new routing method is used - called , A Deep sub-wavelength lithography, (using the 193nm lithography to print 45nm, 32nm, and possibly 22nm integrated circuits), is one of the most fundamental limitations for the continuous VLSI scaling,. Lithography printability is strongly layout dependent, thus routing plays an important role in addressing the overall circuit manufacturability and product yield since it is the last major physical design step before tape out. This paper will discuss some recent advancement of lithography friendly routing from post-routing hotspot fixing (construct by- correction) to during-routing hotspot avoidance (correct-by construction) guided by various lithography metrics.
Keywords:cost metric, hotspot avoidance , hotspot fixing, LFR routing, routing congestion, subwavelength lithography

[1] L. Huang and D. F. Wong, "Optical Proximity Correction (OPC)- Friendly Maze Routing" in Proc. Design Automation Conf., Jun 2004, pp. 186 – 191.

[2] Y.-R. Wu, M.-C. Tsai, and T.-C. Wang, "Maze Routing with OPC Consideratio," in Proc. Asia and South Pacific Design Automation Conf., Jan 2005, pp. 198 – 203.

[3] T.-C. Chen and Y.-W. Chang, "Routability-driven and Optical Proximity Correction-aware Multilevel Full-Chip Gridless Routin," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 6, pp. 1041–1053, Jun 2007.

[4] J. Mitra, P. Yu, and D. Z. Pan, "RADAR: RET-Aware Detailed Routing Using Fast Lithography Simulations" in Proc. Design Automation Conf., Jun 2005, pp. 369 – 372.

[5] T. Kong, H. Leung, V. Raghavan, A. K. Wong, and S. Xu, "Model Assisted Routing for Improved Lithography Robustness," in Proceedings of the SPIE, vol. 6521, Feb 2007, p. 65210D.
[6] M. Cho, H. Xiang, R. Puri, and D. Z. Pan, "Wire Density Driven Global Routing for CMP Variation and Timing," in Proc. Int.
Conf. on Computer Aided Design, Nov 2006, pp. 487 – 492.
[7] T. E. Gbondo-Tugbawa, "Chip-Scale Modeling of Pattern Dependencies in Copper Chemical Mechanical Polishing Process,"
Ph.D. dissertation, Massachusetts Institute of Technology, 2002.
[8] L. He, A. B. Kahng, K. Tam, and J. Xiong, "Design of Integrated-Circuit Interconnects with Accurate Modeling of CMP," in
Proceedings of the SPIE, vol. 5756, Mar 2005, pp. 109–119.
[9] R. Tian, D. F. Wong, and R. Boone, "Model-Based Dummy Feature Placement for Oxide Chemical-Mechanical Polishing
Manufacturability," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 7, pp. 902 – 910, Jul
2001.
[10] M. Cho, H. Xiang, R. Puri, and D. Z. Pan, "TROY: Track Router with Yield-driven Wire Planning," in Proc. Design Automation
Conf., Jun 2007, pp. 55 – 58.

ABSTRACT:An improved technique for FIFO design is to perform asynchronous comparisons between the FIFO write and read pointers that are generated in clock domains and asynchronous to each other. The asynchronous FIFO pointer comparison technique uses fewer synchronization flip-flops to build the FIFO. This method requires additional techniques to correctly synthesize and analyze the design, which are detailed in this paper. To increase the speed of the FIFO, this design uses combined binary/Gray counters that take advantage of the built-in binary ripple carry logic. This FIFO design is used to implement the AMBA AHB Compliant Memory Controller. Which means, Advanced Microcontroller Bus Architecture compliant Microcontroller .The MC is designed for system memory control with the main memory consisting of SRAM and ROM.
Keywords:AMBA, AHB ,FIFO, Gray Counter, ,Memory Controller

[1] Clifford E. Cummings, "Simulation and Synthesis Techniques for Asynchronous FIFO Design," SNUG 2002 (Synopsys Users Group Conference, San Jose, CA, 2002) User Papers, March 2002, Section TB2, 2nd paper. Also available at www.sunburst-design.com/papers
[2] Clifford E. Cummings, "Synthesis and Scripting Techniques for Designing Multi-Asynchronous Clock Designs," SNUG 2001 (Synopsys Users Group Conference, San Jose, CA, 2001) User Papers, March 2001, Section MC1, 3rd paper. Also available at www.sunburst-design.com/papers
[3] Clifford E. Cummings and Don Mills, "Synchronous Resets? Asynchronous Resets? I am So Confused! How Will I Ever Know Which to Use?" SNUG 2002 (Synopsys Users Group Conference, San Jose, CA, 2002) User Papers, March 2002, Section TB2, 1st paper. Also available at www.sunburst-design.com/papers

[4] Frank Gray, "Pulse Code Communication." United States Patent Number 2,632,058. March 17, 1953.

[5] John O'Malley, Introduction to the Digital Computer, Holt, Rinehart and Winston, Inc., 1972, pg. 190.
[6] Peter Alfke, "Asynchronous FIFO in Virtex-II™ FPGAs," Xilinx techXclusives, downloaded from www.xilinx.com/support/techXclusives/fifo-techX18.htm

[5] "Prime Cell AHB SRAM/NOR Memory Controller", Technical Reference Manual, ARM Inc. Building an AMBA AHB compliant Memory Controller Hu Yueli1,2, Yang Ben1,2

[6] Key Laboratory of Advanced Display and System Applications, Ministry of Education,

[7] College of Mechanical and Electronic Engineering and Automation, Shanghai University, Shanghai 200072, China.

ABSTRACT:Applications of the Ant Colony Optimization (ACO) to solve image processing problem with a reference to a new automatic enhancement technique based on real-coded particle ant colony is proposed in this paper. The enhancement process is a non-linear optimization problem with several constraints. The objective of the proposed ACO is to maximize an objective fitness criterion in order to enhance the contrast and detail in an image by adapting the parameters of a novel extension to a local enhancement technique. The feasibility of the proposed method is demonstrated and compared with Genetic Algorithms (GAs) and Particle Swarm Optimization (PSO) based image enhancement technique. The obtained results indicate that the proposed ACO yields better results in terms of both the maximization of the number of pixels in the edges and the adopted objective evaluation. Computational time is also relatively small in the ACO case compared to the GA and PSO case..
Keywords:Ant Colony Optimization, Particle Swarm Optimization, Genetic Algorithms, Image enhancement

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[2] Gonzalez and Woods (2001), Digital Image Processing Edition,567-633, Prentice Hall

[3] B. TirimulaRao, K. VenkatRao, G. KiranSwathi, G. PruthviShanthi, and J. SreeDurga. "A Novel Approach to Image Edge Enhancement Using Smoothing Filters." The Icfai University Journal of Computer Sciences (April 2009), Vol.3, No.2, 37

[4] OzgurBaskan, SonerHaldenbilen, HuseyinCeylan, HalimCeylan. "A new solution algorithm for improving performance of ant colony optimization" of Applied Mathematics and Computation 211(2009) 75-84, ELSEVIER.

[5] Marco Dorigo, Thomas Stutzle. A Brad Book, The MIT Press, Cambridge, Massachusetts, London, England

[6] TirimulaRaoBenela, SreeDurgaJampala, Sathya Harish Villa, BhargaviKonathala. "A Novel Approach to Image Edge Enhancement using Artificial Bee Colony Algorithm for Hybrid Filters" BICA-09, IEEE Conference, Buvaneshwar, ISBN 9784244- 5612-3/09

[7] TirimulaRaoBenela, Suresh Chandra Satapathy, SreeDurgaJampala, Sathya Harish Villa, S Chandra Sekhar. "A Novel Approach to Image Edge Enhancement using Particle Swarm Optimization Algorithm for Hybridized Smoothening Filters" SRC

[8] AleksanderLazinica. "Particle Swarm Optimization" published in Intech, p.cm., ISBN 978-953-7619-48-0

[9] Malik Braik, AlaaSheta, Aladdin Ayesh. "Image Enhancement Particle Swarm Optimization" Proceedings of World Congress on Engineering 2007, Vol 1, WCE 2007, July 2 ISBN 978-988-98671-5-7

[10] Mantas Paulinas and Andruisusinskas " Algorithms Applications For Image Enhancement and Segmentation", ISSN 1392 –124X INFORMATION TECHNOLOGY AND CONTROL, 2007, Vol.36, No.3, 278

ABSTRACT:Design of high speed and low power data path logic systems are one of the most challenging areas of research in VLSI system design. Adder circuit is the main building block in DSP processor. However, Digital adders suffer with the problem of carry propagation delay. To alleviate this problem Carry Select Adder (CSLA) are used in computational unit. Carry Select Adder one of the fastest adder among other. There is scope to reduce the power consumption in the regular CSLA. A simple gate level modification is required of the regular CSLA to reduce the power. This paper proposes modified 40-bit square-root CSLA (SQRT CSLA) architecture. Both the regular and modified 40-bit CSLA are designed with TSMC 0.13-μm CMOS process technology and results are compared with TSMC 0.18-μm CMOS process technology. The proposed design has reduced area and power as compared with the regular SQRT CSLA withy slight increase in the delay. The result analysis shows that proposed CSLA has better performance than conventional CSLA.
Keywords:Low power, DSP processor, CSLA, Power Delay Product, MAC

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[2] B. Ramkumar, H.M. Kittur, and P. M. Kannan, "ASIC implementation of modified faster carry save adder," Eur. J. Sci. Res., vol. 42, no. 1, pp. 53–58, 2010.

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