iosr-JVSP   Volume-1 ~ Issue-4

ABSTRACT:The paper presents a vehicle detection system by locating their headlights and tail lights in the nighttime road environment. The system detects the vehicles light in front of a micro CCD camera assisted vehicle i.e. oncoming & preceding vehicles. Our system automatically controls vehicle's head lights status between low and high beams which avoids the glares for the drivers. The captured frames consist of number of bright objects over dark background. These objects are due to vehicle lamps, road reflection etc. The captured object features are used to train and classify the two classes of lights in vehicles light & other light source. The machine learning based approach, Support Vector Machine (SVM) is used to accomplish this task. The output of the SVM is simply the signed distance of the test instance from the separating hyperplane. The result show the SVM is effective to classify number of lights and it is useful for vehicle validation.
Keywords:Computer vision, Driver Assistance, Image processing, Support Vector Machine, Vehicle detection.

[1] Chun-Che Wang, Shih-Shinh Huang , Li-Chen Fu, Pei-Yun Hsiao, National Taiwan University, Taipei, Taiwan, R.O.C., Driver
Assistance System for Lane Detection and Vehicle Recognition with Night Vision, IEEE Transactions on Intelligent Transportation
Systems, Vol. 3, No. 3, pp 203-209, Sept. 2002.
[2] Ming-Yang Chem , Ping-Cheng Hou, National Chung Cheng University, Min-Hsiung, Chia-Yi, Taiwan, The Lane Recognition and
Vehicle Detection at Night for A Camera-Assisted Car on Highway, Proceedings of the 1003 IEEE, International Conference on
Robotics & Automation, Taipei. Taiwan, September 14-19, 2003.
[3] Yi-Ming Chan, Shih-Shinh Huang, Member, IEEE, Li-Chen Fu, Fellow, IEEE, and Pei Yung Hsiao, Member, IEEE, Vehicle
Detection Under Various Lighting Conditions by Incorporating Particle Filter, Proceedings of the 2007 IEEE Intelligent
Transportation Systems Conference Seattle, WA, USA, Sept. 30 - Oct. 3, 2007.
[4] O'malley R. Glavin, M. and Jones. Connaught Automotive Research Group Department of Electronic Engineering, National
University of Ireland, Galway, Vehicle Detection at Night Based on Tail-Light Detection, ISVCS. 1st International ICST
Symposium on Vehicular Computing Systems. ISVCS2008.3546, E. 2008.
[5] P. F. Alcantarilla, L.M. Bergasa, P. Jim´enez, M. A. Sotelo, I. Parra, D. Fernandez, Department of Electronics. University of
Alcal´a, Alcal´a de Henares (Madrid), Spain, Night Time Vehicle Detection for Driving Assistance LightBeam Controller, 2008
IEEE Transaction, Eindhoven University of Technology Eindhoven, The Netherlands, June 4 -6, 2008.
[6] Peachanika Thammakaroon, Poj Tangamchit Department of Control System and Instrumentation Engineering, Kmg Mongkut's
University of Technology Thonburi, Thailand, Predictive Brake Warning at Night using Taillight Characteristic, IEEE International
Symposium on Industrial Electronics (ISlE 2009).
[7] Steffen Gormer, Dennis Muller, Stephanie Hold, Faculty of Electrical Engineering and Media Technologies, University of
Wuppertal, D-42119 Wuppertal, Germany. Mirko Meuter, and Anton Kummert, Delphi Electronics & Safety Advanced
Engineering D-42119 Wuppertal, Germany. Vehicle Recognition and TTC Estimation at Night based on Spotlight Pairing,
Proceedings of the 12th International IEEE Conference on Intelligent Transportation Systems, St. Louis, MO, USA, October 3 -7, 2009.
[8] Andrea Fossati, CV Lab – EPFL 1015 Lausanne-Switzerland, Patrick Schonmann Cinetis SA 1920 Martigny – Switzerland, Pascal
Fua CV Lab – EPFL 1015 Lausanne- Switzerland, Real-Time Vehicle Tracking for Driving Assistance, Machine Vision and
Applications (ISSN: 1432-1769), 24 Jun 2010.
[9] Ronan O'Malley, Edward Jones, Member, IEEE, and Martin Glavin, Member, IEEE, Rear-Lamp Vehicle Detection and Tracking in
Low-Exposure Color Video for Night Conditions, IEEE Transactions on intelligent transportation systems, vol. 11, no. 2, June 2010.
[10] M. Betke, E. Haritaoglu, and L. S. Davis, Real-time multiple vehicle detection and tracking from a moving vehicle, Mach. Vis.
Appl., Vol. 12, 2000, pp. 69-83.

ABSTRACT:Super-resolution aims to produce a high-resolution image from a set alone or more low-resolution images by recovering or inventing plausible high-frequency image content. Typical approach is try to reconstruct a high-resolution image using the sub-pixel displacements of several low-resolution images, usually regularized by a generic smoothness prior over the high-resolution image space. Throughout this paper, a higher resolution image is defined as an image with more resolving power. Super Resolution consists of two main steps: image registration and image reconstruction. Precise alignment of the input images is one of the important terms. In this paper, we have implemented and tested motion estimation algorithms and image reconstruction algorithms in spatial domain as well as in frequency domain in order to study their analytical parameters and a high resolution image is created by using bicubic interpolation over the prealiased images. Also the experimental as well as analytical results of this paper are successful in spatial domain as per the application of image superresolution.
Keywords:Superresolution, Image registration, Image Reconstruction.

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[3] Julien Mairal, Michael Elad, and Guillermo Sapiro, Senior Member, IEEE , "Sparse Representation for Color Image Restoration",
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[4] F.Sroubek, G.Cristobal and J. Flusser, "Simultaneous super-resolution and blind deconvolution", 4th AIP International Conference
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[5] S. C. Park, M. K. Park, and M. G. Kang, "Super-resolution image reconstruction - a technical overview", IEEE Signal Process. Magazine, vol. 20, pp. 21-36, May 2003
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ABSTRACT: Convolution is fundamental operation of most of the signal processing systems. It is necessity of time to speed up convolution process at very appreciable extent. Here Direct method of computing the discrete linear convolution of finite length sequences is used. The approach is easy to learn because of the similarities to computing the multiplication of two numbers by a pencil and paper calculation. Multipliers are basic building blocks of convolver. Since it dominates most of the execution time, for optimizing the speed, 4×4 bit Vedic multipliers based on Urdhva Tiryagbhyam sutra are used. Convolver has delay of 17.996 ns when implemented on 90 nm process technology FPGA. It also provides necessary modularity, expandability, and regularity to form different convolutions for any number of bits. The coding is done in VHDL (Very High Speed Integrated Circuits Hardware Description Language) for the FPGA , as it is being increasingly used for variety of computationally intensive applications. Simulation and synthesis is done using Xilinx 9.2i.
Keywords: Convolution , FPGA ,Vedic Mathematics

[1] Rashmi Lomte and Bhaskar P.C., "High Speed Convolution and Deconvolution using Urdhva Triyagbhyam " ,2011 IEEE Computer
Society Annual Symposium on VLSI ,p.323 ,July 2011.
[2] John W. Pierre, "A Novel Method for Calculating the Convolution Sum of Two Finite Length Sequences", IEEE transaction on
education, VOL.39, NO. 1, 1996.
[3] Honey Tiwari, Ganzorig ankhuyag, Chan Mo Kim,Yong Beom Cho,"Multiplier design based on ancient Indian Vedic
Mathematics",IEEE,2008 International Soc Design Conference.
[4] Sumit Vaidya, Deepak Dandekar ,"Delay power performance comparison of multipliers in VLSI circuit design", International Journal
of Computer Networks & Communications, Vol 2, No. 4,July 2010.
[5] Chao Cheng , Keshab K. Parhi "Hardware Efficient Fast Parallel FIR Filter Structures Based on Iterated Short Convolution" IEEE,
and, IEEE transaction on circuits and systems, VOL. 51, NO. 8, 2004.
[6] Thomas Oelsner ,"Implementation of Data Convolution Algorithms in FPGAs" http://www.quicklogic.com/images/appnote18.pdf
[7] Abraham H. Diaz, Domingo Rodriguez ,"One Dimentional Cyclic Convolution Algorithms With Minimal Multiplicative Complexity", ICASSP.
[8] Mountassar Maamoun,"VLSI Design for High Speed Image Computing Using Fast Convolution- Based Discrete Wavelet
Transform", Proceedings of the world Congress on Engineering Vol 1,July 2009.
[9] Pandit Ramnandan Shastri, "Vedic Mathematics", Arihant Publications, p.V.

ABSTRACT: This project presents circuit design of a low-power delay buffer. The proposed delay buffer uses several new techniques to reduce its power consumption. Since delay buffers are accessed sequentially, it adopts a ring-counter addressing scheme. In the ring counter, double-edge-triggered (DET) flip-flops are utilized to reduce the operating frequency by half and the C-element gated-clock strategy is proposed. A novel gatedclock- driver tree is then applied to further reduce the activity along the clock distribution network. Moreover, the gated-driver-tree idea is also employed in the input and output ports of the memory block to decrease their loading, thus saving even more power.
Keywords: C- element, delay buffer, first-in-first-out, gated clock, ring counter

[1] Eberle et al., "80-Mb/s QPSK and 72-Mb/s 64-QAM flexible and scalable digital OFDM transceiver ASICs for wireless local area
networks in the 5-GHz band," IEEE J. Solid-State Circuits, vol. 36, no. 11, pp. 1829–1838, Nov. 2001.
[2] M. L. Liou, P. H. Lin, C. J. Jan, S. C. Lin, and T. D. Chiueh, "Design of an OFDM baseband receiver with space diversity," IEE
Proc. Commun., vol. 153, no. 6, pp. 894–900, Dec. 2006.
[3] G. Pastuszak, "A high-performance architecture for embedded block coding in JPEG 2000," IEEE Trans. Circuits Syst. Video
Technol., vol. 15, no. 9, pp. 1182–1191, Sep. 2005.
[4] W. Li and L.Wanhammar, "A pipeline FFT processor," in Proc. Workshop Signal Process. Syst. Design Implement., 1999, pp. 654 –
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[5] N. Shibata, M.Watanabe, and Y. Tanabe, "A current-sensed high-speed and low-power first-in-first-out memory using a
wordline/bitline- swapped dual-port SRAM cell," IEEE J. Solid-State circuits, vol. 37, no. 6, pp. 735–750, Jun. 2002.
[6] Hosain.R, L. D. Wronshi, and albicki.A, 1994. Low power design using double edge triggered flip-flop," IEEE Trans. Very Large
Scale Integr. (VLSI ) Syst., vol.2, no. 2, pp. 261–265.

ABSTRACT: Flip-flops are the major storage elements in all SOC's of digital design. They accommodate most of the power that has been applied to the chip. Flip-flop is one of the most power consumption components. It is important to reduce the power dissipation in both clock distribution networks and flip-flops. The power delay is mainly due to the clock delays. The delay of the flip-flops should be minimized for efficient implementation. The concept of this project is to reduce the power consumption and to increase the speed and functionality of the chip. This project moves around in replacing conventional master-slave based flip flop to a pulse triggered flip flop which acts as a tribute alternate for low power applications. Initially in the critical path the pulse generation controls logic along with SVL function. A simple transistor SVL design is used to reduce the circuit complexity. In this scheme transistor sizes and pulse generation circuit can be further reduce for power saving. Here UMC CMOS 180nm technology is use in SPICE tool to design the proposed structure. This would bring up the result in power saving approximately to 38.4%.
Keywords: Flip-flop, low power,svl

[1] B. Nikolic et al., "Improved sense-amplifier-based flip-flop: Design and measurements," IEEE J. Solid-State Circuits, vol. 35, no.
6, pp. 876–883, Jun. 2000.
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microprocessors," in Int. Symp. Low Power Electron. Des. Tech. Dig.,2001, pp. 147–152.
[5] S. D. Naffziger, "The implementation of the itanium 2 microprocessor,"IEEE J. Solid-State Circuits, vol. 37, no. 11, pp. 1448–
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[8] N.Nedovic, M.Aleksic, V.G. Oklobdzijia, "Conditional Precharge Techniques for Power -Efficient Dual-Edge Clocking" Int. Symp.
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ABSTRACT: This paper present a new design of comparator for flash ADC . The flash ADC is the fastest Application ADC that requires the high speed comparator. The new design consist of sense amplifier and SR Latch ,the combining configuration of design have the considerable stable output which helps in high speed and resolution. The use of SR symmetric latch makes stable output as compared to the conventional SR latch moreover the design has high resolution. This paper has been done in 180 nm and 90nm gpdk in CADENCE VIRTUOSO. For low power application. There are many issues in the design of the comparator, we will discuss those design issues in this paper.

[1] T. N. B. Wicht and D. Schmitt-Landsiedel, "Yield and Speed Optimization a Latch-Type Voltage Sense Amplifier,"Solid-State
Circuits, IEEE Journal of, vol. 39, pp. 1148–1158, July 2004.
[2] E. A. v. T. D. Schinkel, E. Mensink and B. A. Nauta, "A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold
Time," Solid- State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International.
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measurements," Solid-State Circuits, IEEE Journal of, vol. 35, pp. 876–884, June 2000.
[4] Reference /text book ken-martin.

ABSTRACT: In this paper, a simple switched capacitor Digital to Analog Converter (DAC) is presented that exhibits monotonicity and occupies small area. The proposed DAC starts its conversion from the MSB instead of the traditional approach of starting from LSB making it suitable for use in cyclic or successive approximation analog-to-digital converters. The reference voltage is sampled once and appropriate charge is transferred to the output capacitor of the DAC. Some issues relevant to the design and their possible solutions are presented. The DAC is designed for a resolution of 8-bit. Sampling speed is chosen to be 5MS/s and the main emphasis is on low power. This DAC consumes power in the order of microwatt (𝜇𝑊), compare with previous DACs which consumes more power, generally in the order of milliwatts. The output 8-bits along with power dissipation of 493.8 𝜇W has been achieved.

Index Terms—DAC, Folded Cascode, SAR ADC, Transmission gates.

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Circuits and systems, 2002.

ABSTRACT: Design complexity is increasing day by day in modern digital systems. Due to reconfigurable architecture, low non recurring engineering (NRE) and ease of design field programmable gate arrays (FPGA) become a better solution for managing increasing design complexity. Due to scaling trends FPGA uses more transistors which increase the leakage current. FPGAs are well suited for wireless applications since they provide high performance computation together with the capability to adapt to changing communication protocols. So if we are able to reduce the leakage power of an FPGA device, then it can be suitable for use in mobile as well as other low power and battery operated applications..

Keywords -Carry look Ahead adder, field programmable gate arrays (FPGA), ground bounce noise, leakage current, and look up table (LUT).

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