iosr-JVSP   Volume-2 ~ Issue-3

ABSTRACT: At present, the importance of improving a traffic system has become more important than ever before due to the immense number of vehicles on the road. In this paper a unifying philosophy for carrying out different level of image processing has been presented in order to find the best possible outcomes to solve the vision problem at night time. The whole process was done using the low level and mid level image processing algorithms. As there is no fixed method of doing this kind of transformations, in this paper different types of transformations have used to find out the best possible output. There are different types of edge detection techniques in order to detect the substances properly. In case of segmentation, there are different algorithms which can be manipulated according to the purpose. Here we have used some of these techniques to find out the best possible method for this job. Merging with logarithmic and power law transformation this edge detection and segmentation technique produces the output that we have longed for.

Keyword – Image and Video processing, Image Enhancement, Gray Level Transformation, Image Segmentation.

[1] http://www.who.int/violence_injury_prevention/publications/road_traffic/world_report/en/index.html
[2] Bolen J et al. Overview of efforts to prevent motor vehicle-related injury. In: Bolen J, Sleet DA, Johnson V, eds. Prevention of motor vehicle-related injuries: a compendium of articles from the Morbidity and Mortality Weekly Report, 1985–1996. Atlanta, GA, Centers for Disease Control and Prevention, 1997..
[3] http://www.wisegeek.com/what-is-video-processing.htm
[4] Jones, W. ,Keeping cars from crashing, IEEE Spectrum, Vol. 38, No. 9, pp. 40-45. (2001):
[5] Rafael C. Gonzalez, Richard E. Woods ,Digital image processing Second Edition .
[6] http://www.oculist.net/downaton502/prof/ebook/duanes/pages/v8/v8c016.html
[7] http://homepages.inf.ed.ac.uk/rbf/HIPR2/pixlog.htm.
[8] Oge Marques, Practical Image and Video Processing using Matlab,.
[9] Birkhauser, Boston , Jean-Michel Morel and Sergio Solimini ,Variational methods in Image Segmentation , Progress in Nonlinear Differential Equations and Their Applications, Vol 14.
[10] POLAK, M., ZHANG, H. & PI, M.,An evaluation metric for image segmentation of multiple objects. Image and Vision Computing, 27(8):1223-1227. 2009.

ABSTRACT: Leakage power has become an important contributing factor of power for the CMOS circuits in deep sub-micron process. MTCMOS is a very effective technique to reduce the leakage current of circuits in the standby mode. Placing a global sleep device is not practical and sleep device at fine grain level involves more number of sleep transistors and more routing space. Distributed MTCMOS is better technique with self sleep circuit to avoid complexities in routing and sleep distribution network. A simple FFT processor is designed with self sleep buffer using body bias to reduce its standby power. Ccomparisons are made between leakage power for FFT implemented in CMOS and distributed self sleep FFT using the 90nm CMOS technology in cadence tools.

Keywords – FFT, Leakage power, MTCMOS, Sleep device, Standby mode.

[1] Archana Nagda, et.el " Leakage Power Reduction Techniques: A New Approach", International Journal of Engineering Research and Applications, Vol. 2, Issue 2,Mar-Apr 2012, pp.308-312.

[2] C. Long, and L. He, "Distributed sleep transistor network for power reduction," IEEE Trans. VLSI Syst., vol. 12, no. 9,Sep. 2004. [3] K. Shi, D. Howard, "Sleep transistor design and implementation – simple concepts yet challenges to be optimum," in Proc. Int. Symp. VLSI Design, Automation and Test, pp. 1-4, April 2006.

[4] V. Khandelwal and A. Srivastava, "Leakage control through fine-grained placement and sizing of sleep transistors," in Proc. EEE/ACM Int. Conference on CAD, pp. 533-536, 2004.

[5] B. H. Calhoun, F. A. Honore, and A. P. Chandrakasan, "A leakage reduction methodology for distributed MTCMOS," Jour.Solid-State Circuits, vol. 39, no. 5, pp. 818-826, May 2004..

[6] P. Saxena, N. Menezes, P. Cocchini, D. A. Kirkpatrick, "Repeater scaling and its impact on CAD," IEEE Trans. CAD of Integ. Circuits and Syst., vol. 23, no. 4, pp. 451-463, Apr. 2004.

[7] Charbel J. Akl and Magdy A. Bayoumi "Self-Sleep Buffer for Distributed MTCMOS Design" 21st International Conference on VLSI Design, the Center for Advanced Computer Studies (CACS).

[8] T. Esther Rani and Dr. Rameshwara rao,"Design of simple general purpose microprocessor with self sleep buffer", International Journal of Computer Applications, Vol66-No20, March 2013.
[9] www.cmlab.csie.ntu.edu.tw/cml/dsp/training/coding/transform/fft.html

ABSTRACT: In this paper we have analyzed the advantages of using dynamic circuits over static circuits with result oriented example for NAND operation. The different aspects covered under this discussion include power, speed, area, input Capacitance and timing delays calculation. We have also covered the problem of increase in dynamic power dissipation at the dynamic and the output node in dynamic circuits. A circuit is proposed for un-footed dynamic buffer circuit where the power dissipation is reduced from 256μW to 142μW at the output node in the proposed circuit as compared to that in standard dynamic domino logic buffer circuit. Simulation results are obtained using 0.12μm CMOS technology.

Keywords - Dynamic Circuits, Domino Logic, Keeper Circuit, Buffer, Power Dissipation, Skewed Gates

[1] Neil H. E. Weste, David Harris, Aryan Banerjee, "CMOS VLSI DESIGN, Eighth Impression, page no. 226-231, 2009.
[2] Amit Kumar Pandey, Ram Awadh Mishra, Rajendera Kumar Nagaria, "Low Power Dynamic Buffer Circuits," International Journal of VLSI design and Communication Systems(VLSICS), Vol 3, No. 5, October, 2012.
[3] A. K. Pandey, R. A. Mishra, R. K. Nagaria, "Static Switching Dynamic Buffer Circuit,".
[4] Volkan Kursun, Eby G. Friedman, "Speed and Noise Immunity Enhanced Low Power Dynamic Circuits," Name of Journal/ Conference/ Book, Vol x, No. x, pp. x-x, Year.
[5] R. H. Krambeck, C. M. Lee and H. Law, "High-speed compact circuits with CMOS", IEEE Transactions on Journal of Solid State Circuits,vol.17,no.3,pp.614-619,June 1982.
[6] S. Wairya, R. K. Nagaria and S. Tiwari, "Comparative performance analysis of XOR-XNOR function based high speed CMOS full adder circuits for low voltage VLSI design",International Journal of VLSI design and Communication Systems (VLSICS), AIRCC Publication, vol.3, no. 2,pp.221-242, 2012.
[7] Y. J. Ren. ,I. Karlsson and Svensson, "A true single-phase clock dynamic CMOS circuit technique",IEEE Transactions on Solid-State Circuits,vol no. 22,pp.899-901,1987.

ABSTRACT: With the availability of multisensor images in many fields, sensor fusion has emerged as a new and promising research area. Multisensor image data often present complementary information about the region surveyed, so that image fusion provides an effective method to enable comparison and analysis of such data. Image fusion aims at the integration of complementary data to enhance the information content of the imagery, i.e. make the imagery more useful to a particular application.

Keywords - DMWT, fusion, fusion rules.

[1] VARSHNEY, P.K.: "Multisensor data fusion‟, Electron. Conimun. Eng. 1, 1997, 9, (12), pp, 245-253

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[3] BURT, P.J., and KOLCZYNSKI, R.J.: "Enhanced image capture through fusion‟. Proceedings of 4th International Conference on Computer vision, May 1993, Berlin, Germany, pp. 173-182

[4] MALLAT, S.G.: "A theory for multiresolution signal decomposition: The wavelet representation‟, IEEE Trans. Pattern Anal Mach. Intell., 1989, 11, (7), pp. 674-693

[5] LI, H., MANJUNATH, B.S., and MITRA, S.K.: "Multisensor image fusion using the wavelet transform‟, Graph. Models Iniage Process., 1995, 57, (3), pp. 235-245

[6] DAUBECHIES, I.: "The wavelet transform, time-frequency localization and signal analysis‟, IEEE Trans. InJ Theog: 1990, 36, (9), pp. 961-1005

[7] THAM, J.Y., SHEN, L., LEE, S.L., and TAN, H.H.: "A general approach for analysis and application of discrete multiwavelet transforms‟, IEEE Trans. Signal Process., 2000, 48, (2), pp. 457-464 [8] STRELA, V, HELLERS, P.N., STRANG, G., TOPIWALA, P.: and HEIL, C.: "The application of multiwavelet filter banks to image processing‟, IEEE Trans. Image Process., 1999, 8, (4), pp. 548-563

[9] GERONIMO, J.S., HARDIN, D.P., and MASSOPUST, P.R.: "Fractal functions and wavelet expansions based on several functions‟, J1 Approx. Theoy, 1994, 78, (3), pp. 373-401 [10] STRELA, V: "Multiwavelets: theory and application‟. PhD dissertation, Department of Mathematics, Massachusetts Institute of Technology, 1996

ABSTRACT: Images are often corrupted by impulse noise in the procedures of image acquisition and transmission. In this paper, we propose An Efficient VLSI Architecture for Removal of Impulse Noise in Image using edge preserving filter, to achieve low-complexity VLSI architecture. We employ a decision-tree-based impulse noise detector to detect the noisy pixels, and an edge-preserving filter along with mathematical morphological filter to reconstruct the intensity values of noisy pixels. Furthermore, an adaptive technology is used to enhance the effects of removal of random valued impulse noise. Our extensive experimental results demonstrate that the proposed technique can obtain better performances in terms of both quantitative evaluation and visual quality than the previous lower-complexity methods. Moreover, the performance can be comparable to the higher-complexity methods. The VLSI architecture of our design yields a processing rate of about 200 MHz by using TSMC 0.18μm technology. The design requires only low computational complexity and two line memory buffers. Its hardware cost is low and suitable to be applied to many real-time applications.

Keywords - edge preserving filter, Image denoising, impulse noise, impulse detector, image acquisition

[1] R. Giral, L. Martinez-Salamero, and S. Singer, "Interleaved convertersoperation based on CMC," IEEE Trans. Power Electron., vol. 14, no. 4,pp. 643–652, Jul. 1999.

[2] H. Kosai, S. McNeal, B. Jordan, J. Scofield, B. Ray, and Z. Turgut,"Coupled inductor characterization for a high performance interleaved boost converter," IEEE Trans. Magn., vol. 45, no. 10, pp. 4812–4815,Oct. 2009.

[3] C. A. Gallo, F. L. Tofoli, and J. A. C. Pinto, "A passive lossless snubberapplied to the AC–DC interleaved boost converter," IEEE Trans. PowerElectron., vol. 25, no. 3, pp. 775–785, Mar. 2010.

[4] Y. Jang and M. M. Jovanovic, "Interleaved boost converter with intrinsicvoltage-doubler characteristic for universal-line PFC front end," IEEETrans. Power Electron., vol. 22, no. 4, pp. 1394–1401, Jul. 2007.

[5] F. Musavi, W. Eberle, and W. G. Dunford, "A high-performance single-phasebridgeless interleaved PFC converter for plug-in hybrid electricvehicle battery chargers," IEEE Trans. Ind. Appl., vol. 47, no. 4, pp. 1833–1843, Jul./Aug. 2011.

[6] C. A. Gallo, F. L. Tofoli, and J. A. C. Pinto, "Two-stage isolated switch modepower supply with high efficiency and high input power factor,"IEEE Trans. Ind. Electron., vol. 57, no. 11, pp. 3754–3766, Nov. 2010.

[7] M. O'Loughlin, "UCC28070 300-W interleaved PFC pre-regulator designreview," TI Appl. Rep. SLUA479B, Aug. 2008, revised Jul. 2010.

[8] C.-P. Ku, D. Chen, C.-S. Huang, and C.-Y. Liu, "A novel SFVM-M3control scheme for interleaved CCM/DCM boundary-mode boost converterin PFC applications," IEEE Trans. Power Electron., vol. 26, no. 8,pp. 2295–2303, Aug. 2011.2303, Aug. 2011.

[9] Y. T. Chen, S. M. Shiu, and R. H. Liang, "Analysis and design of a zero-voltage-switching and zero-current-switching interleaved boost converter,"IEEE Trans. Power Electron., vol. 27, no. 1, pp. 161–173, 2011.

[10] G. Yao, A. Chen, and X. He, "Soft switching circuit for interleaved boost converters," IEEE Trans. Power Electron., vol. 22, no. 1, pp. 80–86, Jan.2007.

ABSTRACT: This Paper proposed a method of Skewed circuit to avoid the unwanted switching of the controlling operation during the continuation of same level of the signal. In Application where the control model has to check the command signals at beginning of each clock cycle to control the further operation , this types of switching can provide the better potency. In this paper we apply this method on the widely used CMOS technology .All the proposed work is designed & analysed over the DSCH2.7f & Microwind 2.6k.In this paper we compare a full adder using the conventional CMOS and proposed Skewed CMOS on 0.12μm.

Keywords: CMOS, Skew, Microwind, DSCH

[1] Bijan Davari , Robert H.Dennard and Ghavam G.Shaidi"CMOS scaling for high performance and Low power-the next ten year" Proceeding of IEEE, VOL. 83, No.4, April 1995.

[2] Alexandre Solomatnikov, Dinesh Somasekhar, Kaushik Roy and Cheng Kok Koh"Skewed CMOS: Noise-immune high performance low power static circuit family" Computer Design, 2000 International conference on Sep, 2000.

[3] Alexandre Solomatnikov, Dinesh Somasekhar, Naran Sinsantana and Kaushik Roy"Skewed CMOS: Noise-immune high performance low power static circuit family" IEEE Transaction on Very large scale integration (VLSI) system,VOL. 10, No. 4, august 2002.

[4] CMOS vlsi design by Neil H.E. Weste, David Harris, Ayan Banerjee (Pearsion publication), Third Edition.

[5] Microwind and DSCH reference manual, version2.

ABSTRACT: A breadth first trellis decoding algorithm is introduced for application to sequence estimation in digital transmission. The decoding effort adapts to the prevailing noise conditions to yield low average effort. The proposed method of a performance of error correcting in noisy channels to reduce the power dissipation, the decoding speed in much to design a VD for TCM is presented in this paper. VD is used to decode the digital data communications and storage devices without any performance loss. A viterbi decoder uses the viterbi algorithm for decoding a bit stream that has been encoded using Forward error correction based on a code There are other algorithms for decoding a convolutionally encoded stream as well as punctured codes The advandage of VD is errors and correction and digital communication. The pre computation VD could reduce the power consumption by 70% with only 11% reduction of the maximum decoding speed.

Keywords- Convolution codes, Trellis coded modulation(TCM), Threshold,Viterbi decoder , VLSI.

[1]. Jinjin He.Huaping Liu, Zhongfeng Wang. Xinming Huang and Kai Zhang, "High-Speed Low-Power Viterbi Decoder Design for TCM Decoders" – IEEE TRANS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEM, Vol, 20, No.4, April 2012.
[2]. J.He.Z.Wang, and H.Liu, "An efficient 4-d 8PSK TCM decoder architecture." – IEEE Trans, Very Large Scale Integer, (VLSI) Syst., Vol, 18, No.5, pp.808-817, May 2010.
[3]. J.Communications, Networks and Sciences "A Low Power and High Speed Viterbi Decoder Based on Deep Pipelined, Clock Blocking and Hazrds Filtering Int.", 2009, 6, 575-582.
[4]. Rami A.Abdullah, Student Member, IEEE, and Naresh R.Shanbhag, Fellow, IEEE "Error-Resilient Low-Power Viterbi Decoder Architectures" December 2009.
[5]. Charan Langton "Trellis Coded Modulation (TCM) Intuitive Guide to Principles of Communications", 2004.
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[8]. F.Chan and D.Hacoun, "Adaptive Viterbi decoding of convolutional codes over memoryless channels," IEEE transaction on Communications, Vol. 45, No.11, pp.1389-1400, Nov, 1997.
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ABSTRACT: In this paper we are presenting a Half-Subtractor using Adaptive Voltage Level (AVL) technique consuming less power than the conventional one .The main objective is to design that half subtractor using either of the two adaptive voltage level(AVL) techniques to reduce the sub threshold leakage current which plays a very important role in the reduction of power dissipation. We can bring down the value of total power dissipation by applying the AVLG (adaptive voltage level at ground) technology in which the ground potential is increased and AVLS (adaptive voltage level at supply) in which supply potential is raised. Also the reduced transistor count add to the further lowering of power consumption of the realized Half-Subtractor circuit which is optimized at .90 micron technology using AVL technique. The AVL technique based Half-Subtractor compared to conventional one based on power consumption, speed, layout area and propagation delay is more preferred. The circuit is simulated on microwind and DSCH in .90 micron CMOS technology.

Keywords- Half-Subtractor, AVL techniques, DSCH, microwind simulator, VLSI circuit and low power

[1] Deepa Sinha, Tripti Sharma, K. G. Sharma, Prof. B. P.Singh, Ultra Low Power 1-Bit Full Adder (ijca 2011).

[2] Neil H. E. Weste, Principal of CMOS VLSI Design, Pearson Education, 2003

[3] Prof. Yusuf Leblebici, CMOS Digital Integrated Circuits, TMH, 2003.

[4] W. Wolf, Modern VLSI Design- Systems on Silicon, Prentice Hall, Taur, Y, and Ning, T. H. 1998.Fundamentals of modern VLSI devices. Cambridge university press, New York.

ABSTRACT: Arithmetic logic unit is the core of any CPU that can be part of a programmable reversible computing device such as a quantum computer. The major concern for ALU design ,using normal gates is heavy power consumption. The main reason for power consumption is the normal irreversible gates. In order to ensure low power design constraint a new type of gates called reversible gates were introduced. In reversible gates the number of inputs is equal to the number of outputs and there is a one to one mapping between the inputs and outputs. Here in this paper we discuss the design of a low power ALU using reversible gates and its implementation on FPGA.

Keywords – ALU, FPGA, Reversible gates, Reversible logic, Spartan.

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