iosr-JVSP   Volume-3 ~ Issue-1

ABSTRACT:Our method uses the built-in scan-chain in a VLSI circuit to drive it with the minimum leakage vector when it enters the sleep mode. Using these scan registers eliminates the area and delay overhead of the additional circuitry that would otherwise be needed to apply the minimum leakage vector to the circuit. We show how the proposed technique can be used for several different scan-chain architectures and present the experimental results on the MCNC91 benchmark circuits. General Terms- CMOS VLSI, sub-threshold, Leakage current

Keywords: Scan-in, Scan-out, Scan-chain structure

[1] Ferre, A. and Figueras, J., "Characterization of Leakage Power in CMOS Technologies", IEEE International Conference on Electronics, Circuits and Systems, Vol. 2, 1998, pp. 85 -188.

[2] Cheng, Z., Johnson, M., Wei, L. and Roy, K., "Estimation of Standby Leakage Power in CMOS Circuits Considering Accurate Modeling of Transistor Stacks", ISLPED 98, pp. 239-244.

[3] Johnson, M., Somasekhar, D. and Roy, K., "Models and Algorithms for Bounds in CMOS Circuits", IEEE Transactions on CAD of Integrated Circuits and Systems, Vol. 18, No. 6, June 1999, pp. 714-725.

[4] Ye, Y., Borkar, S., and De, V., "A New Technique for Standby Leakage Reduction in High-Performance Circuits," Symposium on VLSI Circuits, 1998, pp. 40-41.

[5] Bobba, S. and Hajj, I., "Maximum Leakage Power Estimation for CMOS Circuits", Proceedings of the IEEE Alessandro Volta Memorial Workshop on Low-Power Design, 1999, pp. 116 -124.

[6] Johnson, M., Somasekhar, D. and Roy, K., "Leakage Control With Efficient Use of Transistor Stacks in Single Threshold CMOS ", Proceedings of the 36th Design Automation Conference (DAC), June 1999, pp. 442-445.

[7] Halter J., and Najm, F., "A Gate-level Leakage Power Reduction Method for Ultra Low Power CMOS Circuits, IEEE Custom Integrated Circuits Conference, 1997, pp. 475-478

. [8] Gupta S. "Digital System Testing", to be published by Cambridge University Press

[9] Abramovici, M., Breuer, M.A., Friedman, A.D.," Digital Systems Testing and Testable Designs", Computer Science Press, New York, 1995

[10] Abdollahi, A.; Fallah, F.; Pedram, M., "Runtime mechanisms for leakage current reduction in CMOS VLSI circuits" Low Power Electronics and Design, 2002. ISLPED '02. Proceedings of the 2002 International Symposium on, 2002, Page(s): 213 -218

ABSTRACT:Text in images provides essential information of the image content and thus text detection is fundamental to indexing of an image database. The existing methods do not provide effective results for images with different text orientation and text sizes. This paper presents an edge based algorithm that uses connected component analysis for handling non-horizontal text strings and Gaussian scale space for multi-scale texts. The experimental results show the effectiveness of this approach in detecting text blocks irrespective of its orientation and size.

Keywords: Text detection, Text orientation, Text size, connected component analysis, Gaussian scale space

[1] K. Jung, K.I. Kim and A.K. Jain, "Text information extraction in images and video: a survey", Pattern Recognition, 37, 2004, pp.977-997.
[2] Gatos B., Pratikakis I., and Perantonis S.J. (2005), "Text detection in indoor/outdoor scene images", First International Workshop on Camera-based Document Analysis and Recognition (CBDAR‟05), Aug. 29, Seoul, Korea, pp. 127-132.
[3] K. Sobottka, H. Bunke and H. Kronenberg, "Identification of Text on Colored Book and Journal Covers", In Proc. ICDAR 1999, pp. 57.
[4] T.Pratheeba, Dr.V.Kavitha and S.Raja Rajeswari, "Morphology Based Text Detection and Extraction from Complex Video Scene", International Journal of Engineering and Technology Vol.2(3), 2010, 200-206.
[5] Q. Ye, Q. Huang, W. Gao and D. Zhao, "Fast and robust text detection in images and video frames", Image and Vision Computing 23, 2005, pp. 565-576.
[6] D. Crandall, S. Antani and R. Kasturi (2003), "Extraction of Special Effects Caption Text Events from Digital Video", Int J Doc Anal Recog 5(2–3):138–157, 2003.
[7] Lindeberg, Tony, "Principles for automatic scale selection", In: B. Jähne (et al., eds.), Handbook on Computer Vision and Applications, volume 2, pp 239--274, Academic Press, Boston, USA, 1999.
[8] http://dasl.mem.drexel.edu/alumni/bGreen/www.pages.drexel.edu/_weg22/can_tut.html

ABSTRACT: This paper presents design of quaternary half adder and full adder based on multi valued logic.Adders are one of the important part of the processing element and hence it has a focus of research.Therefore implementation of adders using multi valued logic can prove to be very useful.The proposed half adder and full adders are designed with the help of transmission gate. These half adder and full adder are verified by simulation and appear to have very low power dissipation.

Keywords -Multi-Valued Logic, Quaternary Logic,Adders

[1] EleanDubrova, "Multiple-Valued Logic in VLSI: Challenges and Opportunities"Computer

[2] T.Hlguchl and M.Kameyama,"Synthesis of multiplevalued logic networks based on tree type universal logic modules",Proc. Of 5th Int. Symponisum on multiple-valued logic,Bloomington ,pp.121-130.

[3] Scott Hauck,"Asynchronous design Methodologies:An Overview", Proceedings of the IEEE. Vol.83

[4] S. Hurst, "Multiple-valued logic -its status and its future", IEEE trans.On Computers. Vol. C-33, no.12, pp. 1984

[5] M. Kameyama, "Toward the Age of Beyond-BinaryElectronics and Systems", Proc. of IEEE Int. Symp. On Multiple-Valued Logic, 1990. [

6] Hanyu, M. Kameyama, "A 200 MHz pipelined multiplierusing 1.5V-supply multiple valued MOS current-modecircuits with dual-rail source-coupled logic", IEEE Journal of Solid-State Circuits vol.30, no.11, 1995.

[7] B. Radanovic, M. Syrzycki, "Current-mode CMOS adders using multiple-valued logic", Canadian Conference on Electrical and Computer Engineering,1996

[8] J. Shen et al., "Neuron-MOS current mirror circuit and itsapplication to multi-valued logic", IEICE Trans. Inf. &Syst. E82-D,5 pp.940-948, 1999.

[9] D. H. Y. Teng, R. J. Bolton, "A self-restored current-mode CMOS multiple-valued logic design architecture", 1999 IEEE pacific Rim Conf. on Communications, Computers and Signal Processing (PASRIM'99), pp. 436- 439,1999. [10] F. Wakui and M. Tanaka, "Comparison of Binary Full Adder and Quaternary Signed-Digit Full Adder using High-Speed ECL", International Symposium on Multiple Valued Logic, pp. 346-355,1989

ABSTRACT: Audio signal classification system analyzes the input audio signal and label the signal to a class. The categorization can be done on the basis of pitch, loudness, rms value of signal etc. The signal classifier analyzes the content of the audio format thereby extracting information about the content from the audio data. A number of spectral and temporal features and Mel Frequency Cepstral Coefficients are used for classification purposes. In this paper the implementation of the audio signal classification using Suport Vector Machine (SVM) is presented. Finally the confusion matrix and overall accuracy has been studied in order to evaluate performance of the classification system.

Keywords: Audio feature extraction, loudness, Mel Frequency Cepstral Coefficients, pitch, spectral centroid, spectral flux, spectral sparsity, and spectral roll off, SVM

[1]. Gordon Wichern, JiachenXue, Harvey Thornburg ,Brandon Mechtley, and Andreas Spanias, "Segmentation, Indexing, and Retrieval for Environmental and Natural Sounds," IEEE Trans. Audio, Speech, And Language Processing, Vol. 18, No. 3, March 2010
[2]. Stavros Ntalampiras, IlyasPotamitis and Nikos Fakotakis" Sound Classification based on Temporal Feature Integration" 4th International Symposium on Communications,Control and Signal Processing, ISCCSP 2010, Limassol, cyprus, 3-5 March 2010.
[3]. T. Foote, "Content-based retrieval of music and audio,"Multimedia Storage and Archiving Systems II, Proc. Of SPIE, vol. 3229, pp. 138–147, 1997.
[4]. Lu, G., & Hankinson, T." A technique towards automatic audio classification and retrieval". In 4th International Conference on Signal Processing. Beijing. (Retrieved November 3), 2002,

ABSTRACT: presents an energy efficient successive-approximation-register (SAR) analog-to-digital converter (ADC) for biomedical applications.For low-power applications designer needs to come up with a compromise among speed, resolution and speed power.To reduce energy consumption, a charge redistribution technique is used along with auto zero technique for comparator offset cancellation.The power consumptions of the capacitive digital-to-analog converter (DAC), latch comparator, and digital control circuit of the proposed ADC are lower than those of a conventional SAR ADC.CMOS technology in such a way that the total power is minimized while medium sampling rate and 8 bit resolution are achieved.

IndexTerms: Analog-to-digital converters (ADCs), CMOS analog integrated circuits, low power, offset,autozero,low supply voltage, successive approximation. I. Introduction In the last few

[1] Jens Sauerbrey, Doris Schmitt-Landsiedel, Roland Thewes, "A 0.5V, 1μW Successive Approximation ADC", IEEE Journal of Solid State Circuit, IEEE 2002.

[2] Jiren Yuan and Christer Svensson," A 10-bit 5-MS/s Successive Approximation ADC Cell Used in a 70-MS/s ADC Array in 1.2- pm CMOS", Ieee Journal Of Solid-State Circuits, Vol. 29, No. 8, August 1994.

[3] David A. Johns and Ken Martin ,"Analog Integrated Circuit Design"2nd Ed. 2002 John Wiley & Sons(ASIA) Pvt. Ltd. Singapore.

[4] P. E. Allen, Holberg, CMOS Analog Circuit Design (New York Oxford Uni. Press.2004)

[5] Jens Sauerbrey, Doris Schmitt-Landsiedel, Roland Thewes, "A 0.5V, 1μW Successive Approximation ADC", IEEE Journal of Solid State Circuit, IEEE 2002.

[6] National Semiconductor Article – ABC's of ADC's by Nicholas Gray, November 24 2003.

[7] V. Peluso, P. Vancorenland, A. Marques, M. Steyaert, and W. Sansen, "A 900mV 40μW Switched Opamp ΔΣ Modulator with 77dB Dynamic Range", ISSCC Digest of Technical Papers, pp. 68-69, p. 414, 1998

[8] R. J. Baker, Li H. W., D. E. Boyce, CMOS Circuit Design, Layout, and Simulation (IEEE Press)

[9] F. Maloberti: "Data Converters"; Springer-Verlag, 2007, ISBN 9780387324852.

ABSTRACT: This paper proposes Digital clock synchronization using cyclic rotation algorithm (CRA). By using cyclic rotation algorithm we can adjust the clock delays. The dynamic locking is done through clock synchronization, it means matching the clock frequencies. It consist cyclic shift register(CSR). Its operating frequency range is 50MHz and 300MHz.

Keywords: cyclic shift register(CSR), conventional synchronous mirror delay (CSMD), clock synchronizing, dynamic phase error.

[1] Kuo-Hsing Cheng IEEE, Kai-Wei Hong, Chi-Fa Hsu, and Bo-Qian Jiang "An All-Digital Clock Synchronization Buffer With One Cycle Dynamic Synchronizing", IEEE transactions on vlsi systems, VOL. 20, no.10, october2012
[2] R. J. Yang and S. I. Liu, "A 40–550 MHz harmonic-free all-digital delay-locked loop using a variable SAR algorithm," IEEE J. Solid- State Circuits, vol. 42, no. 11, pp. 361–373, Nov. 2007
[3] B. G. Kim, L. S. Kim, K. I. Park, Y. H. Jun, and S. I. Cho, "DLL with jitter reduction techniques and quadrature phase generation for DRAM interfaces," IEEE J. Solid-State Circuits, vol. 44, no. 5, pp. 1522–1530, May 2009.
[4] D. Shin, W. J. Yun, H. W. Lee, Y. J. Choi, S. Kim, and C. Kim, "A 0.17–1.4 GHz low-jitter all digital DLL with TDC-based DCC using pulse width detection scheme," in Proc. Euro. Solid-State Circuits Conf., 2008
[5] J. S. Wang, C. Y. Cheng, J. C. Liu, Y. C. Liu, and Y. M. Wang, "A duty-cycle-distortion-tolerant half-delay-line low-power fast-lock-in all-digital delay-locked loop," IEEE J. Solid-State Circuits, vol. 45, no. 5, pp. 1036–1047, May 2010
[6] P. Bhoraskar and Y. Chiu, "A 6.1-mW dual-loop digital DLL with 4.6-ps RMS jitter using window-based phase detector," in Proc. IEEE Asian Solid-State Circuits Conf., 2007
[7] Jung, G. Jung, J. Song,M. Y. Kim, J. Park, S. B. Park, and C. Kim, "A 0.004mm2- portable multiphase clock generator tile for 1.2-GHz RISC microprocessor," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 55, no. 2, pp. 116–120, Feb. 2008
[8] K. Sung and L. S. Kim, "A high-resolution synchronous mirror delay using successive approximation register," IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 1997–2004, Nov. 2004

ABSTRACT: Signal processing today is performed in vast majority of systems for ECG analysis and interpretation. The objective of ECG signal processing is manifold and comprises the improvement of measurement accuracy and reproducibility and the extraction of information not readily available from the signal through visual assessment. In many situations, the ECG is recorded during ambulatory or strenuous conditions such that the signal is corrupted by different types of noise, sometimes originating from other physiological process of the body. Hence noise reduction represents another important objective of ECG signal processing. The paper mainly focuses on implementing the present day trends and procedures in the processing of ECG signals using software (MATLAB). The implementation process helps us to understand the drawbacks and difficulties of such methods and gives us an opportunity to work out towards finding a better solution. Such a solution would satisfy the scope of improvement expected in the technologies, used at present. Keywords: ECG, baseline wander, powerline interference, QRS detection

[1] Wiley Encyclopedia of Biomedical Engineering,2006 edition by John Wiley & Sons, Inc.
[2] The official website of matlab – www.mathworks.com( for the matlab documentation)
Design of ECG Signal Acquisition and Processing System (2012). Zeli Gao; Jie Wu; Jianli Zhou; Wei Jiang; Lihui Feng

[4] Implementation of ECG signal processing and analysis techniques in digital signal processor based system (2009). Balasubramaniam, D.; Nedumaran, D.

[5] New aspects in ECG signal processing using adaptive filters (2011). Tudosa, I.; Adochiei, N.I.; Ciobotariu, R.

[6] Processing ECG signals using rational function systems (2012).Locsi, L.; Kovacs, P.

[7] Evaluation of novel ECG Signal Processing on Quantificatiojn of Transient Ischemia amd Baseline wander suppression (2007). Kostic, M.N.; Fakhar, S.; Foxall, T.; Drakulic, B.S.; Krucoff, M.W.

[8] Image processing on ECG chart for ECG signal recovery (2009).Shen, T.W.; Laio, T.F.

[9] ECG signal acquisition and analysis for telemonitoring (2010).Plesnik, E.; Malgina, O.; Tasič, J.F.; Zajc, M.

[10] Power- line Interference Detection and Suppression in ECG Signal Processing (2008). Yue-Der Lin; Yu Hen Hu

ABSTRACT: Leakage power reduction is extremely important in the design of scaled CMOS logic circuits. The dominant leakage components of such circuits are the sub threshold leakage and the thin-oxide gate leakage. This paper describes an efficient leakage reduction method that considers both these components, and is based on the selective insertion of control points. The selection is based on the leakage reduction potential and the delay insensitivity of the candidate gates. Simulations on the ISCAS85 benchmark circuits show that this method results in 67% leakage reduction with no speed degradation when control points are added to 93% of the gates compared to the leakage of the baseline circuit whose inputs have been subjected to the minimum leakage vector.

Index Terms: Control point insertion, leakage current reduction, leakage sensitivity (LS), low power design, minimum leakage vector (MLV).

[1] S. Borker, ―Design challenges of technology scaling,‖ IEEE Micro, vol. 9, no. 4, pp. 23–29, Jul.–Aug. 1999.

[2] S.23 Mukhopadhyay, A. Raychowdhury, and K. Roy, ―Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling,‖ in Proc. Design Automation Conf., Jun. 2003, pp. 169–174.

[3] M. Johnson, D. Somasekhar, and K. Roy, ―Models and algorithms for bounds on leakage in CMOS circuits,‖ IEEE Trans. Computer-Aided Des. Integr. Circuits Syst., vol. 18, no. 6, pp. 714–725, Jun. 1999.

[4] A. Abdollahi, F. Fallah, and M. Pedram, ―Runtime mechanisms for leakage current reduction in CMOS VLSI circuits,‖ in Proc. ISLPED, Aug. 2002, pp. 213–218.

[5] J. Kao, A. Chandrakasan, and D. Antioniadis, ―Transistor sizing issues and tool for multi-threshold CMOS technology,‖ in Proc. Design Automation Conf., 1997, pp. 409–414.

[6] L. Wei, Z. Chen, M. Johnson, K. Roy, and V. De, ―Design and optimization of low voltage high performance dual threshold CMOS circuits,‖ in Proc. 35th Design Automation Conf., Jun. 1998, pp. 489–494.

[7] S. Narendra, S. Borker, V. De, D. Antoniadis, and A. P. Chandrakasan, ―Scaling of stacked effect and its application for leakage reductions,‖ in Proc. ISLPED, 2001, pp. 195–200.

[8] D. Lee, W. Kwong, D. Blaauw, and D. Sylvester, ―Analysis and minimization techniques for total leakage considering gate oxide leakage,‖ in Proc. Design Automation Conf., Jun. 2003, pp. 175–180.

[9] S. Mukhopadhyay, C. Neau, R. T. Cakici, A. Agarwal, C. H. Kim, and K. Roy, ―Gate leakage reduction for scaled devices using transistor stacking,‖ IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 11, no. 4, pp. 716–730, Aug. 2003.

[10] K. Chopra, S. B. K. Vrudhula, and S. Bhardwaj, ―Efficient algorithms for identifying the minimum leakage states in CMOS combinational logic,‖ in Proc. 17th Int. Conf. VLSI Design, Jan. 2004, pp. 240–245.

ABSTRACT: Image compression is one of the major image processing techniques that are widely used in medical, automotive, consumer and military applications. Discrete wavelet transforms is the most popular transformation technique adopted for image compression. In this brief, by operating the shifting and addition in parallel, an error-compensated adder-tree (ECAT) is proposed to deal with the truncation errors and to achieve low-error and high-throughput discrete wavelet transform (DWT) design. Instead of the 12 bits used in previous works, 9-bit distributed arithmetic-precision is chosen for this work so as to meet peak-signal-to-noise-ratio (PSNR) requirements. Thus, an area-efficient DWT core is implemented to achieve 1 Gpels/s throughput rate with gate counts of 22.2 K for the PSNR requirements outlined in the previous works. This design is twice faster than the reference design and is thus suitable for applications that require high speed image processing algorithms.

Key words: Distributed arithmetic (DA)-based, error-compensated adder-tree (ECAT), 2-D Discrete wavelet transforms (DWT).

[1] David S. Taubman, Michael W. Marcellin - JPEG 2000 – Image compression, fundamentals, standards and practice", Kluwer academic publishers, Second printing - 2002.

[2] G. Knowles, "VLSI Architecture for the Discrete Wavelet Transform," Electronics Letters, vo1.26, pp. 1184-1185,1990.

[3] M, Vishwanath, R. M. Owens, and M. 1. Irwin, "VLSI Architectures for the Discrete Wavelet Transform," IEEE Trans. Circuits And Systems II, vol. 42, no. 5, pp. 305-316, May. 1995.

[4] AS. Lewis and G. Knowles, "VLSI Architectures for 2-D Daubechies Wavelet Transform without MUltipliers".Electron Letter, vo1.27, pp. 171-173, Jan 1991.

[5] K.K. Parhi and T. Nishitani "VLSI Architecture for Discrete Wavelet Transform", IEEE Trans. VLSI Systems, vol. 1, pp. 191-202, June 1993. [6] M. Vishwanath, R.M. Owens and MJ. Irwin, "VLSI Architecture for the Discrete Wavelet Transform", IEEE Trans. Circuits and Systems, vol. 42, pp. 305-316, May 1996.

[7] C. Chakrabarti and M. Vishwanath, "Architectures for Wavelet Transforms: A Syrvey", Journal of VLSI Signal Processing, Kulwer, vol.lO, pp. 225-236,1995.

[8] David S. Tabman and Michael W. Marcelliun, "JPEG 2000 – Image Compression, Fundamentals, Standards and Practice", Kulwer Academic Publishers, Second printing 2002.

[9] CharilaosChristopoulos, AthanassiosSkodras, and TouradjEbrahimi - "THE JPEG2000 STILL IMAGE CODING SYSTEM – AN OVERVIEW", Published in IEEE Transactions on Consumer Electronics, Vol. 46, No. 4, pp. 1103-1127, November 2000.

[10] MajidRannani and Rajan Joshi, "An Overview of the JPEG2000 Still Image Compression Standard", Signal Processing, Image Communication, vol. 17, pp. 3-48, 2002.

ABSTRACT: Analog to Digital Converters (ADCs) which are having importance in interface between analog and digital world are key design blocks and are currently adopted in many application fields to improve digital systems, which achieve superior performances with respect to analog solutions. This paper presents the comparative analysis of ADCs based on different performance parameters i.e. speed, technology used, power consumption, signal to noise ratio, bandwidth and dynamic & static characteristics. Various examples of ADC applications can be found in data acquisition systems, measurement systems and digital communication systems also imaging, instrumentation systems. The main aim of this paper is to provide comparison between different performance parameters for all ADCs & analyzing the better results & performance in future.

Keywords: Analog to Digital Converter, Flash, Sigma-Delta (Σ -Δ), Pipeline, Quantization, Sampling.

[1] W. Kester, The Data Conversion Handbook New York: Elsevier, 2005, Analog Devices, Inc.
[2] C. Quintans et al. ―A methodology to teach advanced A/D Converter, combining digital signal processing and microelectronics
perspectives,‖ IEEE Tranactions on Education, vol.53, no. 3, pp.471 -483,Aug. 2010.
[3] D. A. Rauth and V.T. Randal, ―Analog –to-digital conversion,‖ IEEE Instrum. Meas. Mag., vol. 8, no. 4, pp. 44-55, Oct. 2005.
[4] P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design 2nd Edition, Oxford University Press, ISBN 0-19-511644-5.
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Engineering New Mexico State University Las Cruces, New Mexico, pp.1-74,10th October,2005.
[6] Sunghyun Park, Yorgos Palaskas, Ashoke Ravi2, Ralph E. Bishop, and Michael P. Flynn, "A 3.5 GS/s 5-b Flash ADC in 90 nm
CMOS," IEEE 2006 Custom Integrated Circuits Conference (CICC), pp. 489-492, 2006.
[7] Sreehari Veeramachanen, A. Mahesh Kumar, Venkat Tummala,and M.B. Srinivas "Design of a Low Power, Variable-Resolution
Flash ADC", IEEE 22nd International Conference on VLSI Design,pp.117-122, 2009.
[8] Jun-Xia Ma, Sai-Weng Sin, Seng-Pan U , R.P.Martins, "A Power Efficient 1.056 GS/s Resolution-Switchable 5-bit/6bit Flash ADC
for UWB Applications," IEEE ISCAS, pp.4305-4308,2006.
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Transactions on very large scale integration (VLSI) systems, VOL. 18, NO. 3, March 2010

ABSTRACT: The designing of high performance analog circuits is getting more & more challenging with the centre of attention towards reduced supply voltages. In this paper Telescopic OTA is chosen for designing signal processing circuits because it has high gain, high speed and power consumption of this OTA is comparatively low. Signal processing circuits includes Oscillators, Amplifiers and Filters. In Oscillator, Colpitts oscillator is designed and for amplification purpose, Instrumentation Amplifier is designed. Signal processing circuits are incomplete without filters so Chebyshev Low Pass Filter is designed. Design and simulation is done on Tanner EDA 13.0. Keywords: Gain bandwidth product (GBW), Signal processing circuits, Operational Transconductance Amplifier (OTA), Tanner EDA, Transconductance.

[1]. Shireen T. Sheikh, D.J. Dahigoankar, Hemant Lohana. "Comparative Analysis of CMOS OTA" IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) ISSN: 2319 – 4200, ISBN No. : 2319 – 4197 Volume 1, Issue 3 (Nov. - Dec. 2012).
[2]. Razavi Behzad, Design of Analog CMOS Integrated Circuits ( Tata McGraw-Hill .2002).
[3]. Choong Yul Cha,Sang Gug Lee "A Complementary Colpitts Oscillator in CMOS Technology", IEEE Transaction on Microwave theory & Techniques, Vol.53 No.3 March 2005.
[4]. A. Bakker, K.Thiele and J. H. Huijsing, "A CMOS Nested-Chopper Instrumentation Amplifier with 100-nV Offset", IEEE Journal of Solid-State Circuits, vol. 35, December, 2000.
[5]. Neha Gupta, Meenakshi Suthar, Sapna Singh, Priyanka Soni "Active Filter Design Using Two OTA based Floating Inductance Simulator" International Journal of VLSI & Signal Processing Applications, Vol.2,Issue 1, Feb 2012