iosr-JVSP   Volume-3 ~ Issue-2

ABSTRACT:The most important issues in video watermarking are invisibility of the watermark and the resilience of watermarking to attacks. The area of video watermarking has focused primarily on the problem of robustness to geometric attacks, while discounting the problem of more sophisticated attackers. So to improve the robustness of watermark for A new digital watermarking algorithm, for based on LDPC coding ,to embedded the watermark in videos that insert information in the side view, unlike the regular approaches that insert on the frames. Video watermarking technology has applied image watermarking technology to individual frames of a video. The implemented watermarking system operates in the spectrum domain where a subset of the discrete wavelet transform (DWT) coefficients is modified by the watermark without using the original image during watermark extraction. The quality of watermark is evaluated by taking into account the trade-off between the chip-rate and the rate of LDPC codes.

Keywords: Digital Video watermarking, LDPCEncoder and LDPC Decoder, Robust watermarking, DWT

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ABSTRACT: Monte Carlo based SSTA serves as the golden standard against the alternative SSTA algorithms. The efficient implementation of MC-SSTA is performed by repeatedly executing ordinary STA using a set of randomly generated delay samples. The FPGA device is used as a target device onto which the RTL description is mapped, which acts as a dedicated STA engine. We leverage the path level and gate level parallelisms and the power optimizations of normal distribution random number generators based on central limit theorem. The accuracy is compared with the Mersenne Twister and Box Muller Methods which are high quality random number generators.

Keywords: FPGA, Linear feedback shift register, Monte Carlo, SSTA.

[1] S. R. Nassif, A. J. Strojwas, and S. W. Director, "A methodology for worst-case analysis of integrated circuits," IEEE Trans. CAD, vol. 5,no. 1, pp. 104–113, Jan. 1986.

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ABSTRACT: The uninterrupted development of memory market has experienced a new face since the beginning of the 21st century due to the emergence of pc markets such as Laptop, Server PC, Tablet and Smart phones. This paper demonstrates the implementation of intelligent high performance memory access technique of DDR3 SDRAM. This paper discusses the full architecture of DDR3 SDRAM controller with minimum accessible time. It is designed to achieve high performance memory access with faster read and write. Keywords - Architecture of DDR3 controller, DDR3, High geared access, RAM Controller, SDRAM

[1] K. Sireesha, S.Upender, Design of High Speed DDR3 SDRAM Controller, International Journal of Engineering Research and Applications (IJERA), Vol. 1, Issue 3, pp.969-973.
[2] A.B. Smith, C.D. Jones, and E.F. Roberts, A high performance DDR3 SDRAM Controller, International Journal of Electrical and Electronics Engineering (IJEEE), Volume-1, Issue-1, 2011.
[3] Zuber Basha Shaik, Akurathi Srinivasarao, Design of DDR3 SDRAM Controller for achieving high Speed read Operation, International Journal of Systems Algorithms & Applications (IJSAA), Volume 2, Issue 1, January 2012.
[4] DDR3 SDRAM Specification (JESD79-3E), JEDEC Standard, JEDEC solid state technology association, July 2010.
[5] 2Gb DDR3 SDRAM features, Micron Technology, Inc.( http://www.micron.com).

ABSTRACT: A novel method develops a built-in self-detection and correction (BISDC) architecture for motion estimation computing arrays(MECAs).Based on the error detection & correction concepts of biresidue codes, any single error in each processing element in an MECA can be effectively detected and corrected online using the proposed BISD and built-in self-correction circuits. Performance analysis and evaluation demonstrate that the proposed BISDC architecture performs well in error detection and correction with minor area i.e single error bit detection and correction . an advanced model has been proposed for multi bit detection using efficient adder implementation .A comparision is performed between efficient adder and processing element resultant .

Keywords: Data recovery, error detection, motion estimation, reliability, residue-and-quotient (RQ) code.

[1]. Chun-lung Hsu, chang-Hsin Cheng, and Yu Liu, "Built- in self-detection/correction Architecture for Motion Estimation Computing Arrays", IEEE Transcations on Very Large Scale Integration (VLSI) systems, VOL.18, NO.2, February 2010, pp.319-324.

[2]. Thammavarapu R.N Rao, Member, IEEE, "Biresidue Error-Correcting Codes for Computer Arithmetic", IEEE Transactions on computers, VOL. C-19, NO. 5, May 1970, pp.398-402.

[3]. Meihua GU, Ningmei YU, Lei ZHU, Wenhua JIA, "High Throughput and Cost Efficient VLSI Architecture of Integer Motion Estimation for H.264/AVC", Journal of Computational Information Systems 7:4 (2011), pp.1310-1318.

ABSTRACT: In this paper we are going to modify the Schmitt Trigger based SRAM for the purpose of more reduced power & area than the existing type of designs as well as the new design which is combined of virtual grounding with read Error Reduction Logic is compared with the existing technologies & the nanometer technology is also improved for the purpose of much improved reduction of area & power factors than the Schmitt Trigger based SRAM Designs the simulations were done using microwind & DSCH results

Key words: CMOS, DSCH, SCHMITT- TRIGGER, SRAM, MICROWIND.

[1] Mizuno, H. and T. Nagano, Driving source-line cell architecture for sub-1-V high-speed low-power applications. Solid-State Circuits, IEEE Journal of, 1996.31(4): p. 552-557.

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[5] J. P. Kulkarni, K. Kim and K. Roy "A 160mV robust Schmitt trigger based sub threshold SRAM," IEEE J. Solid-State Circuits, vol.42,no.10, pp.2303-2313, Oct.2007. [6] Bo, Z., et al. A Sub-200mV 6T SRAM in 0.13um CMOS.inSolid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International. 2007.

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ABSTRACT: This work presents a glitch improved design of a 12-bit fully differential current source resistor string hybrid digital-to-analog converter (DAC) achieved by incorporating a swing reduced driver (SRD) circuit in the existing design. The results show that this design achieves a 13.26 % improvement in glitch reduction in comparison with the original version. The physical layout of the glitch improved design DAC is accomplished within a design area of 489.4 μm x 117 μm or 57260 μm2.

Keywords: Hybrid DAC, Glitch

[1] M.T.S. Ab-Aziz, A. Marzuki, and Z.A. Abdul Aziz, 12-Bit Pseudo-differential Current-source Resistor-string Hybrid DAC, Journal of Circuits, Systems, and Computers (JCSC), 20(4), 2011, 709-725.

[2] A.D. Grasso, C.A. Mirabella, and S. Pennisi, CMOS current-steering DAC Architectures based on the triple-tail cell, International Journal of Circuit Theory and Application, 36(3), 2008, 233-246.

[3] I. Myderrizi, and A. Zeki, A High-Speed Swing Reduced Driver Suitable for Current-Steering Digital-to-Analog Converters, Proceedings of the European Conference on Circuit Theory and Design, 2009, 635-638.

[4] P. Aliparast, and N. Nasirzadeh, Very high-speed and high-accuracy current-steering CMOS D/A converter using a novel 3-D decoder, Analog Integrated Circuits and Signal Processing, 60(3), 2009, 195-204.

[5] C. Joo, S. Kim, and K. Yoon, A Low Power l2-Bit 80MHz CMOS DAC Using Pseudo-Segmentation, Proceedings of the 18th ACM Great Lakes symposium on VLSI, 2008, 219-222. [6] S. Sarkar, and S. Banerjee, An 8-bit 1.8V 500 MSPS CMOS Segmented Current Steering DAC, Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI, 2009, 268-273.

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[8] F-Ji. Luo, Y-S. Yin, Liang S-Q. Liang, M-L. Gao, Current Switch Driver and Current Source Designs for High-speed Current-steering DAC, 2nd International Conference on Anti-counterfeiting, Security and Identification, 2008, ASID 2008, 2008, 364-367.

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ABSTRACT: Stenography is the art of hiding secret information in other information and transmitting via wires or through free space. Many variants to transfer the secret image already exist currently but further advancements of digital technology has made the transfer much more effective and faster without tampering the original data. In this paper, we propose a method that encodes a secret image in Grey scale imageinto another set of values and then merged into the container image which is an RGB image and transmitted to the desired location. The image containing the secret image hardly differs from the original container image, which makes decoding the original image difficult.

Keywords:Image Hiding, Secret Sharing, Stenogaphy

[1] Secret image sharing by Chih-Ching Thein,Ja-chen Lin.

[2] An overview of image Stenography by T.Morkel, J.H.P. Eloff, M.S.Olivier

[3] SteganPEG Stenography+JPEG by V.Lokeswara Reddy, Dr.A.Subramanyam, Dr.P.Chenna Reddy

[4] Some New methodologies for Image Hiding using Stenographic Techniques by Rajesh Kumar Tiwari and Gadadhar Sahoo

ABSTRACT: This paper focuses on a new enhanced noise-tolerant dynamic circuit design technique. The effectiveness of this technique is demonstrated by means of HSPICE level 49 simulations for two and four input AND gate. Noise immunity improvement of proposed technique is compared with previous techniques [1]. Simulation results show that the proposed technique has a very good improvement in the noise tolerance and the ANTE-delay quotient over the conventional dynamic logic circuits and decrease in power consumption with less performance degradation than existing ones for AND gates.

Keywords: Keeper transistor; Noise immunity; Dynamic circuits; Domino Logic; CMOS ; ANTE; EANTE; PDN;

[1] O. Gonzalez-Diaz, M. Linares-Aranda, and F. Mendoza-Hernández, "A Comparison Between Noise-Immunity Design Techniques for Dynamic Logic Gates" Proceedings of the 49th IEEE International Midwest Symposium on Circuits and Systems, 2006, pp. 484-488, 2006

[2] L. Ding and P. Mazumder, "On circuit techniques to improve noise immunity of CMOS dynamic logic" IEEE Trans. VLSI Syst., vol. 12, no. 9, pp. 910-925, Sept. 2004.

[3] F. Mendoza-Hernandez, M. Linares, A. Sanchez, and V. Champac, "A new technique for noise-tolerant pipelined dynamic digital circuits" Proceedings of the IEEE International Symposium on Circuits and Systems, 2002., vol. 4, no. 4, pp. IV-185-IV-188, May 2002.

[4] Ganesh Balamurugan, and Naresh R. Shanbhag, "The Twin-Transistor Noise-Tolerant Dynamic Circuit Technique", IEEE Journal of Solid-State Circuits, Vol. 36, No. 2, Feb. 2001, pp. 273-280

[5] You-Gang Chen, I-Chyn Wey and An-Yeu (Andy) Wu, "A New Noise-Tolerant Dynamic Circuit Design with Enhanced PDP Performance under Low SNR Environment", IEEE Asian Solid-State Circuits Conference, 2006, Nov. 2006, pp.295-298.

[6] F. Mendoza-Hernandez, "Design techniques to enhance noise tolerance in CMOS digital dynamic circuits" Ph.D Thesis, INAOE, Puebla, Mexico, Aug. 2003.

[7] Lei Wang and Naresh r. Shanbhag "An Energy-efficient NOISE-TOLERANT Dynamic circuit technique" IEEE transactions on circuits and systems-ii vol. 47, no. 11, november 2000.

[8] Suresh kumar pittala, Swajeeth Pilot Panchangam, and Dr. A. Jhansi Rani, "Reliability prediction for low power adiabatic logic families" International Journal of Recent Technology and Engineering, vol. 1, no. 3, pp. 116-121, 2012.
[9] N.M. Sai Krishna, P. Suresh Kumar, G. Varalakshmi, "A Extensive Active Noise Cancellation from Cardiac Signals using a Constrained Stability Least Mean Square Algorithm" International Journal of Electronics & Communication Technology, vol . 3, issue 4, ver. 3 oct. to dec. 2012

ABSTRACT: In this paper we describe a very simple and efficient method for the détection and recognition of the Malayalam text from colour natural scene images taken by a mobile phone camera. Malayalam text detection, skew correction of the detected text ,text segmentation and character recognition are the important steps in text understanding from natural scene images. Text understanding in natural scene image is very important for many purposes such as assistance system for the visually challenged persons and text translation in foreign countries. The experimental results show that our method can successfully extracts and recognizes the text with low complexity and therefore can be used in the mobile devices which have limited capability.

Keywords : Skew angle estimation, text detection, text segmentation, text recognition.

[1]. Toan Nguyen Dinh, Jonghyun Park and GueeSang Lee," Korean Text Detection and Binarization in Colour Signboards," International Conference on Advanced Language Processing and Web Information Technology, 2008
[2]. Nobuyuki Otsu, "A Threshold Selection Method from Gray-Level Histogram". IEEE Transaction on Systems, Man and Cybernetics (1979).
[3]. Ayatullah Faruk Mollah, Subhadip Basu, and Mita Nasipuri ,"Text/Graphics Separation and Skew Correction of Text Regions of Business Card Images for Mobile Devices ," Journal of computing, volume 2, issue 2, February 2010, ISSN 2151-9617
[4]. Vikas J Dongre , Vijay H Mankar "Devnagari document segmentation using histogram approach" Department of Electronics & Telecommunication, Government Polytechnic, Nagpur, India
[5]. Nadira Muda, Nik Kamariah Nik Ismail, Siti Azami Abu Bakar, Jasni Mohamad ZainFakulti Sistem Komputer & Kejuruteraan Perisian, "Optical Character Recognition By Using Template Matching " University Malaysia Pahang Karung Berkunci 12, 25000 Kuantan, Pahang

ABSTRACT: This paper presents a description of the work done on phonetic speech analysis. The work aims in generating phonetic codes of the uttered speech in training-less, human independent manner. This work is guided by the working of ear in response to audio signals. The Devnagri script inspires the work presented. The Devnagari script classifies and arranges 46 phonemes in a scientific manner based on the process of its generation. The work at present focuses on identifying the class (varna) of the phoneme as specified by the Devnagari script. More work is needed to identify the variant of the class identified. Phoneme code thus generated can be used in an application specific way. This work also explains and proves the scientific arrangement of the Devnagari script. This work tries to segment speech into phonemes and identify the phoneme using simple operations like differentiation,zero crossing, FFT. In the phoneme recognition research literature, no work has been reported on Devnagari speech processing . So we consider our work to be the first such attempt in this direction. The process involves extraction of some distinct characteristics of individual phonemes by utilizing Fourier transforms. The system is speaker-independent and is moderately tolerant to background noise.

Keywords - Devnagari script, Phonetic speech analysis, Phoneme recognition, Speech to Text conversion.

[1] Phonetic Speech Analysis for Speech to Text Conversion, 2008 IEEE Region 10 Colloquium and the Third International Conference on Industrial and Information Systems, Kharagpur,INDIA December 8 -10, 2008.

[2] A new approach for phoneme segementation of speech signals,Douglas O'Shaughnessy Ladan Golipour, in Proceedings of Interspeech ,Antwerp,Belgium,August 2007. Books: [1] AshtadhyaeeBhashyam ; Swami Dayanand Saraswati

[2] Digital Processing of Speech Signals; Rabiner, Schafer; Pearson Education.

[3] Discrete Time Speech Signal Processing; Quatieri; Pearson Education.

[4] A Speaker independent digit recognition system, L. Rabiner , M.Sambur.

[5] Robust entropy based endpoint detection, Jia-lin Shen, Jei-Weih Hung,Lin-Shan Lee.