iosr-JVSP   Volume-4 ~ Issue-3 ~ May-June 2014

ABSTRACT: Digital Signal Processing (DSP) blocks are the backbone of all multimedia applications and Low Power is an imperative requirement for portable multimedia devices handling different signal processing algorithms and architectures. Human beings can capture useful information even if the output is having some error. Thus, we need not produce exact numerical outputs. Previous researches provide the error resiliency through Voltage Over Scaling (VOS) by various algorithms and architectures to reduce the errors. In this paper, the logic complexity reduction is proposed by using approximate adders which is obtained by reducing the number of transistors without reducing the quality of the output signal. Simulation results shows the power reduction by using approximate adders compared to the actual full adder cells.
Keywords: Approximate Adders, Digital Signal Processing, Low Power, Mirror Adders.

[1] W. Dally, J. Balfour, D. Black-Shaffer, J. Chen, R. Harting, V. Parikh, J. Park, and D. Sheffield, "Efficient embedded computing," Computer, vol. 41, no. 7, pp. 27–32, Jul. 2008.
[2] P. Kulkarni, P. Gupta, and M. Ercegovac, "Trading accuracy for power with an underdesigned multiplier architecture," in Proc. 24th IEEE Int. Conf. VLSI Design, Jan. 2011, pp. 346–351.

[3] R. Hegde and N. Shanbhag, "Energy-efficient signal processing via algorithmic noise-tolerance," in Proc. IEEE/ACM Int. Symp. Low Power Electron. Design, Aug. 1999, pp. 30–35.
[4] R. Hegde and N. R. Shanbhag, "Soft digital signal processing," IEEE Trans. Very Large Scale Integr. Syst., vol. 9, no. 6, pp. 813–823, Jun. 2001.
[5] B. Shim, S. Sridhara, and N. Shanbhag, "Reliable low-power digital signal processing via reduced precision redundancy," IEEE Trans. Very Large Scale Integr. Syst., vol. 12, no. 5, pp. 497–510, May 2004.

ABSTRACT: Adders are one of the widely used digital components in digital integrated circuit design. Addition is the basic operation used in almost all computational systems. Therefore, the efficient implementation and design of arithmetic units requires the binary adder structures to be implemented in an equally efficient manner. A ripple carry adder has smaller area but less speed. A carry look-ahead adder is faster though its area requirements are high. Carry select adders (CSLA) lie in middle. In this work a novel carry select adder using Binary Excess Converter (BEC) is proposed. It provides good compromise between cost and performance thereby establishing a proper trade-off between time and area complexities. In this work Tanner EDA is used for the comparison of all adders – Ripple carry adder, Bitwise carry select adder, Square root carry select adder, proposed carry select adder using BEC.
Keywords: Carry Select Adder, Binary Excess Converter, Fast Adder.

[1]. B. Ramkumar and Harish M Kittur, ―Low-Power and IEEE transactions on very large scale integration (VLSI) systems vol. Area-Efficient Carry Select Adder‖.20, no. 2, February 2012.
[2]. Wonhak Hong, Rajashekhar Modugu, and Minsu Choi, Efficient Online Self-Checking Modulo Multiplier Design IEEE transactions on computers September 2011.
[3]. Mariano Aguirre-Hernandez, ―CMOS Full-Adders for Energy-Efficient Arithmetic Applications‖ IEEE transactions on very large scale integration (VLSI) Systems June 2010.
[4]. B.Ramkumar, Harish M Kittur and P.Mahesh Kannan, ―ASIC Implementation of Modified Faster Carry Save Adder‖, European Journal of Scientific Research, vol.42 no.1, pp.53-58, 2010.
[5]. Y. He, C. H. Chang, and J. Gu, ―An area efficient 64-bit square root carry-select adder for low power applications,‖ in Proc. IEEE Int. Symp. Circuits Syst., 2005, vol. 4, pp. 4082–4085.

ABSTRACT: (MB-OFDM) Multi-Band Orthogonal Frequency Division Multiplexing is a suitable solution for implementation of high speed data transmission in ultra wideband spectrum by dividing the spectrum into available multiple bands. In MB-OFDM system the most important part is base band of transmitter. In this paper introduced the structure of MB-OFDM system transmitter and the design of transmitter baseband based on FPGA is described in detail. Quartus2 which allow the synthesis of Vhdl code on to Alter's FPGA chip or Xilinx's ISE suit for Xilinx's FPGA chip. The results show that all designed modules has achieved the expected purpose both in precision and resource.
Keywords: OFDM,UWB,Scrambler,encoder,puncturer,Interleaver,QPSK,IFFT

[1]. Implementation of MB-OFDM Transmitter based on FPGA 978-1-4244-1708-7/08c 2008 IEEE Xu Jinsong, Lu Xiaochun, Wu Haitao, Bian Yujing, Zou Decai, Zou Xiaolong, Wang Chaogang.
[2]. Anuj Batra, et al., ―Design of a Multiband OFDM System for Realistic UWB Channel Environments ‖, IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 52, NO. 9, SEPTEMBER 2004.
[3]. ISO/IEC, ―Information technology Telecommunications and information exchange between systems — High Rate Ultra Wideband PHY and MAC Standard‖, 26907, Mar.2007, pp 15-59.
[4]. J. Balakrishnan, A. Batra, A. Dabak, A multi-band OFDM system for UWB communication, IEEE Conference on Ultra Wideband Systems and Technologies, 2003, pp. 354–358.
[5]. Yangheng, et al., ―FPGA / CPLD latest practical technical guidelines‖Tsinghua University Press.2005.pp.1-5..

ABSTRACT: Code Division Multiple Access (CDMA) is a multiple access technique widely used in cellular and military communication systems. In Direct Sequence Spread Spectrum (DSSS) communications, data samples are embedded inside Pseudo Noise code (PN code) prior to transmission. Synchronization of this unique code with the incoming data samples forms an important step in data recovery. Single Dwell Serial Search (SDSS) and Matched Filtering are some of types of the CDMA code synchronization techniques. This paper presents design and implementation of Recursive Digital Matched Filter (RDMF) for code synchronization in CDMA. From design summary, it is observed that with RDMF, lesser hardware is utilized compared to the conventional methods. And also, a modification in despreading steps is proposed for achieving reduced Bit Error Rate (BER) performance
Keywords: Synchronization, Digital matched filter, Component reuse

[1]. Sanjay Kumar Jaiswal, Kumkum Maurya, Dheeraj Jain, Vijayendra Maurya, Design of DS-CDMA transceiver using BPSK modulation\Demodulation, World Applied Sciences Journal 16, Special issue on recent trends in VLSI design, Sep, 2012.
[2]. Andrea Goldsmith, Wireless communication, (2nd edition, Cambridge University press, 2005, 383–386)
[3]. Hong Gil Kim, Iickho Song, Sun Yong Kim, Jooshik Lee, PN code acquisition using nonparametric detectors in DS/CDMA systems, Signal processing, vol 80, issue 4, 2000.
[4]. Yi Wan and Zhongping Chen, A Novel Synchronization Method for DS CDMA Systems, IEEE International Wireless Communications and Mobile Computing Conference (IWCMC), 2012, 596-601.
[5]. STEL-2000A data sheet (Intel Corporation, Dec 15, 1999).

ABSTRACT: FPGA Robotics is commonly used in a VANTER Robotics and space. An efficient solar power FPGA Robotic designs contains low power consumption and improved batteries life. The advantage of a rover in which most of the supplied energy is reduced by a photo voltaic (PV) panel. However the solar panel powered rover introduces the concept of using FPGA for intelligent power management system. The rover has assisted coupled an assisted suspension mechanism this prevents a manipulator arm the rover from having to minimize solar panel generated power and allows it to dust solar panel surface. The robot uses a control algorithm of maximum power point (MPP) aimed at maximizing system supplied power for PV modules designs of its mechanical structure and its simulation results are presented by ModelSim.
Key words: Field Programmable Gate Array (FPGA), VANTER, Photo voltaic (PV) panel, Rover, MPPT

[1]. de J Mateo Sanguino, T.; Gonzalez Ramos, J.E., "Smart Host Microcontroller for Optimal Battery Charging in a Solar-Powered Robotic Vehicle," Mechatronics, IEEE/ASME Transactions on , vol.18, no.3, pp.1039,1049, June 2013.
[2]. Hsu-Chih Huang; Ching-Chih Tsai, "FPGA Implementation of an Embedded Robust Adaptive Controller for Autonomous Omnidirectional Mobile Platform," Industrial Electronics, IEEE Transactions on, vol.56, no.5, pp.1604, 1616, May 2009.
[3]. Masoum, M. A S; Badejani, S.M.M.; Fuchs, E.F., "Microprocessor-controlled new class of optimal battery chargers for photovoltaic applications," Power Engineering Society General Meeting, 2004. IEEE, vol., no., pp.1489 Vol.2,, 10-10 June 2004.
[4]. Koutroulis, E.; Kalaitzakis, K.; Voulgaris, N.C., "Development of a microcontroller-based, photovoltaic maximum power point tracking control system," Power Electronics, IEEE Transactions on, vol.16, no.1, pp.46,54, Jan 2001

[5]. Zhihua Qu; Jing Wang; Plaisted, C.E., "A new analytical solution to mobile robot trajectory generation in the presence of moving obstacles," Robotics, IEEE Transactions on , vol.20, no.6, pp.978,993, Dec. 2004.

ABSTRACT: Dual-tone multi-frequency(DTMF) is an international signaling standard for telephone digits(number buttons). These signals are used in touch-tone telephones as well as many other areas. Since analog devices are rapidly changing with digital devices, digital DTMF decoders become more important. The subject of this paper is to build a dual-tone multi-frequency(DTMF) signal detector. There are many algorithms for DTMF detection, and among all of them the chosen one is Goertzel's algorithm. It is one of the simplest algorithms of all and it is very often used in practical realizations. The simulation of this algorithm is done in MATLAB and outputs of this test are given in this paper.
Keywords: Pulse dialing,Tone dialing, Push button tone dialing,Digital frequency spectrum, Fast fourier spectrum, Goertzel algorithm, Energy threshold.

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ABSTRACT: Wireless sensor networks is a distributed and non-transferable resource. Over time, variations in energy availability would likely to arise. Protocols will be similar to routing trees may concentrate energy handling at certain nodes. Differences in energy harvestshould arising from environmental variations, such as if one node is in the form of cluster and another is in the shade, can pro- duce variations in charging rates and battery levels. We propose a novel approach for mobile users to collect the network-wide large data. The routing node structure of data collection is additively updated with the group of the mobile user. With this approaches, we only perform a limited modification to update the routing structure while the routing performance is bounded and controlled compared to the optimal performance. The proposed protocol is easy to implement. shows that the proposed scalable in maintenanceexpenses, performs efficiently in the routing performance, provides continuous data delivery during the user movement. We implement the proposed protocol an ns2 simulator to verify the efficiency of our proposed protocol.

[1]. E. Hamida and G. Chelius, "Strategies for Data Dissemination to Mobile Sinks in Wireless Sensor Networks," IEEE Wireless Comm., vol. 15, no. 6, pp. 31-37, Dec. 2008.
[2]. S. Olariu and I. Stojmenovic, "Design Guidelines for Maximizing Lifetime and Avoiding Energy Holes in Sensor Networks with Uniform Distribution and Uniform Reporting," Proc. IEEE INFOCOM, 2006.
[3]. X. Li, A. Nayak, and I. Stojmenovic, "Sink Mobility in Wireless Sensor Networks," Wireless Sensor and ActuatorNetworks, A. Nayak, I. Stojmenovic, eds., Wiley, 2010.
[4]. B. Mamalis, D. Gavalas, C. Konstantopoulos, and G. Pantziou, "Clustering in Wireless Sensor Networks," RFID and Sensor Networks: Architectures, Protocols, Security and Integrations, Y. Zhang, L.T. Yang, J. Chen, eds., pp. 324-353, CRC Press, 2009.
[5]. G. Chen, C. Li, M. Ye, and J. Wu., "An Unequal Cluster-Based Routing Protocol in Wireless Sensor Networks," Wireless Networks, vol. 15, pp. 193-207, 2007.

ABSTRACT: Digital signal processors (DSPs) are very important in various engineering disciplines. Fast multiplication is very important in DSPs for convolution, Fourier transforms etc .In this paper a fast method for multiplication based on ancient Indian Vedic mathematics is used in FIR filter design .The proposed Vedic multiplier is based on Vedic multiplication sutras. Vedic multiplication based on Urdhva tiryakbhyam sutra. This algorithm is applied to digital arithmetic and multiplier architecture is formulated. The coding is done in VHDL (very high speed integrated circuits hardware description language) and synthesis is done using Xilinx ISE series. This Vedic multiplier can bring about great improvement in DSP performance.
Keywords: Urdhva tiryakbhyam, Vedic Multiplier, FIR, VHDL

[1]. 1S. S. Kerur, 1Prakash Narchi, 1Jayashree C N, 2Harish M Kittur and 3Girish V A "Implementation of Vedic Multiplier for Digital Signal Processing" International Conference on VLSI, Communication & Instrumentation (ICVCI) 2011
[2]. Jagadguru Swami Sri Bharati Krisna Tirthaji Maharaja, Vedic Mathematics: Sixteen Simple Mathematical Formulae from the Veda, Delhi (1965).
[3]. H. Thapliyal and M. B. Shrinivas and H. Arbania, "Design and Analysis of a VLSI Based High Performance x Low Power Parallel Square Architecture", Int. Conf. Algo. Math.Comp. Sc., Las Vegas, June 2005, pp. 72-76.
[4]. P. D. Chidgup kar and M. T. Karad, "The Imp lementation of Vedic Algorithms in Digital Signal Processing", Global J. of Engg. Edu, vol.8, no.2, 2004.
[5]. Shamim Akhter,"VHDL Implementation Of Fast NXN Multiplier Based On Vedic Mathematics", Jay p ee Institute of Information Technology University, Noida, 201307 UP, INDIA, 2007 IEEE.

ABSTRACT: This paper describes the implementation of an 8-bit Vedic multiplier using fast adder enhanced in terms of propagation delay when compared with conventional multiplier. In our design of 8 bit Vedic multiplier using fast adder, we have utilized 8-bit barrel shifter which requires only one clock cycle for 'n' number of shifts. The design of 8 bit Vedic multiplier using barrel shifter is implemented and verified using FPGA and ISE Simulator. The core used here was implemented on Altera Cyclone® II 2C20 FPGA device software. The propagation delay between 8 bit Vedic multiplier using barrel shifter using barrel shifter and using fast adder comparison was extracted from the synthesis report and static timing report as well. The design which is implemented here could achieve propagation delay of 6.781ns using barrel shifter block in base selection module and multiplier of architecture used. In our project, we make a comparison between performance analysis of 8 bit Vedic multiplier using barrel shifter and using fast adder.
Keywords: Fast adder, Barrel shifter, base selection module, Propagation delay, power index determinant

[1]. U.C.S.I. P.Kumar, S.Goud A2, A.Radhika,2013: "FPGA Implementation of high speed bit Vedic multiplier using barrel shifter‟, ICEETS Journal, 14-17.
[2]. H. M. Kamboh, S. A. Khan,2012 "FPLA Implementation of Fast Adder‟, ICCCT journal, 1324-1327.
[3]. J. S. S. B. K. T. Maharaja, Vedic mathematics, Delhi: MotilalBanarsidass Publishers Pvt Ltd,(2010).
[4]. M. Ortiz, F. Quiles, J.Hormigo, F.J. Jaime, J. Villalba, E. L. Zapata, 2009 "Efficient implementation of carry-save adders in FPGAs‟,ICASSAP journal, 207-210.
[5]. P.Saha, A Banerjee, P. Bhattacharyya, A.Dandapat, 2011,"High speed ASIC design of complex multiplier using vedicmathematics‟,IJERA journal, 3, 237-241.