iosr-JVSP   Volume-4 ~ Issue-3 ~ May-June 2014

ABSTRACT: This paper presents the realization of area efficient architecture using Distributed Arithmetic with Offset Binary Coding (DA-OBC) for implementation of Finite Impulse Response (FIR) Filter. Area complexity in the algorithm of Finite Impulse Response Filter is mainly caused by multipliers. Among the multiplierless techniques of FIR Filter, Distributed Arithmetic is most preferred area efficient technique. In this technique partial products of filter coefficients are precomputed and stored in Lookup Table (LUT) and the filtering is done by shift and accumulate operations on these partial products. However, the scale of the LUT will increase exponentially with the co-efficient. If the co-efficient is small, it is very convenient to realize. While the coefficient is large, it will take up a lot of storage resources of FPGA and reduce the calculation speed. The paper presents the improvement of the DA algorithm by reducing the LUT size and delay using Offset Binary Coding Algorithm. The design based on Altera EP2S15F484C3 Chips is synthesized under the integrated environment of Quartus II 9.1. The result of simulation and test shows that Offset Binary Coding greatly reduces the FPGA hardware resources and the high speed filtering is achieved compared to conventional DA Algorithm.
Keywords: Finite Impulse Response (FIR); Distributed Arithmetic (DA); Lookup Table (LUT); Offset Binary coding (OBC); Field Programmable Gate Arrays (FPGA).

[1]. Mariusz Rawski, Pawel Tomaszewicz, Henry Selvaraj and Tadeusz Lub, "Efficient Implementation of Digital Filters with use of Adavanced Synthesis Methods Targeted FPGA Architecture", 8th Euromicro Conference on digital system design (DSD'05), IEEE Computer Society, 2005.
[2]. S.K. Mitra, "Digital Signal Processsing – a computer Based Approach", TATA McGraw Hill, Second edition, pp. 427-432,2008.
[3]. M.Yamada and A.Nishihara, "High – Speed FIR Digital Filter with CSD coefficients Implemented on FPGA" , in Proceedings of IEEE Design Automation Conference, 2001, pp.7-8.
[4]. Martinez – Peiro, J.Valls, T. Sansaloni, A.P. Pasual, and E.I.Boemo, " A Comparison between Lattice, cascade and Direct Form FIR filter structures by using a FPGA Bit – Serial DA Implementation", in proceeding of IEEE International Conference on Electronics, Circuits and Systems, 1999, Vol.1.pp.241-244.
[5]. S.S.Jeng, H.C.Lin, and S.M.Chang, " FPGA implementation of FIR filter using M-bit parallel distributed Arithmetic", IEEE ISCAS'2006, pp.875-878.

ABSTRACT: In recent years, there has been a growing need for Successive Approximation Register (SAR) Analog-to-Digital Converter in medical application such as pacemaker. The demand for long battery life-time in these applications poses the requirement for designing ultra-low power SAR ADCs. The project involves custom design and implementation of 8 bit successive approximation ADC for low power and low frequency signals. The ADC would comprise of a SAR Logic, DAC, a comparator and a sample and hold circuit. The DAC would be designed to reduce the systematic and the symmetric errors using the hierarchical symmetrical switching. The main motivation is to implement design of capacitor array DAC and achieve high speed with medium resolution using 60nm technology. The advantage is matching of capacitor can be achieved better then resistor. The market and cost analysis says current SAR ADC has better future. Here we are using spice backend design Tool.
Keywords: SAR ADC, SAR Logic, Comparator, Low Power, high speed.

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ABSTRACT: Fast Fourier Transform (FFT) processing is one of the key procedures in popular Orthogonal Frequency Division Multiplexing (OFDM) communication systems. Structured pipeline architectures, low power consumption, high speed and reduced chip area are the main concerns in this VLSI implementation. In this paper, the efficient implementation of FFT/IFFT processor for OFDM applications is presented. The processor can be used in various OFDM-based communication systems, such as worldwide interoperability for Microwave access (Wi-Max), Digital Audio Broadcasting (DAB), Digital Video Broadcasting-Terrestrial (DVB-T). We adopt single-path delay feedback architecture. To eliminate the Read Only Memories (ROM's) used to store the twiddle factors, this proposed architecture applies a reconfigurable complex multiplier to achieve a ROM-less FFT/IFFT processor and to reduce the truncation error we adopt the fixed width modified booth multiplier. The three Processing Elements (PE's), Delay-Line (DL) buffers are used for computing IFFT. Thus we consume the low power, lower hardware cost, and high efficiency and reduced chip size.
Keywords: FFT, IFFT, OFDM, Modified Booth Multiplier.

[1]. Chu yu, Mao-Hsu Yen " A Low power 64-point
[2]. FFT/IFFT Processor for OFDM Applications" IEEE Transactions on Consumer Electronics,Vol. 57, Feb 2011
[3]. N.Kirubanandasarathy, Dr.K.Karthikeyan," VLSI Design of Mixed Radix FFT Processor for MIMIOFDM in Wireless Communication", 2011 IEEE Proceedings.
[4]. FahadQureshi and Oscar Gustafson,"TwiddleFactor Memory Switching Activity Analysis of Radix-22 and Equivalent FFT Algorithms", IEEE Proceedings, April 2010.
[5]. Jianing Su, Zhenghao Lu, "Low cost VLSI design of a flexible FFT processor", IEEE Proceedings, April 2010.
[6]. He Jing, Ma Lanjaun, XuXinyu, "A Configurable FFT Processor", IEEE proceeding 2010.
[7]. M.Merlyn, "FPGA Implementation of FFT Processor with OFDM Transceiver", 2010 IEEE proceeding.
[8]. "A Radix based Parallel pipelined FFT processor for MB- OFDM UWB system, "Nuo Li and N.P.vanderMeijs, IEEE Proceedings, 2009.

ABSTRACT: This paper introduces a test pattern generator (TPG) in order to use in built-in self-test(BIST). MSIC TPG generates multiple single input change (MSIC) vectors in a pattern, i.e., each vector applied to a scan chain is an SIC vector. With the help of reconfigurable Johnson counter and a scalable SIC counter its easy to generate a class of minimum transition sequences. The proposed TPG is flexible to test-per-scan schemes. A theory is developed to represent and analyze the sequences and to extract a class of MSIC sequences. Analysis results show that the produced MSIC sequences have the favorable features of uniform distribution, minimum transitions, and low input transition density. The Performances of the designed MSIC TPG and the circuit under test are evaluated. Simulation results shows that it can save delay time and power. It also achieves the target fault coverage without increasing the test length.
Keywords: Built-in self-test (BIST), minimum delay, multiple single-input Change (MSIC), test pattern generator (TPG).

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ABSTRACT: In this paper a detailed study of the effect of the phase of noise has been done on 6T SRAM cell. The 6T SRAM has been subjected to different combinations of noises at the storage nodes and the read ability and write ability of the SRAM cell is examined considering different noise voltage levels. It is found that the effect is different under different combinations of the phases of the noise voltages.
Keywords: SRAM, noise, phase, combination

[1]. Naveen Verma, Anantha P. Chandrakasan, A 65nm 8T Sub-Vt SRAM Employing Sense-Amplifier Redundancy: Proc. Of International Solid State Circuits Conference, 2007, 328-329
[2]. Jaydeep P. Kulkarni, Keejong Kim, Sang Phill Park and Kaushik Roy,Process Variation Tolerant SRAM Array for Ultra Low Voltage Aplications: Proc. Of DAC2008, 2008, 108-113
[3]. Y. Wang, H. Ahn, U. Bhattacharya, T. Coan, F. Hamzaoglu, W. Hafez, C.-H. Jan, P. Kolar, S. Kulkarni, J. Lin, Y. Ng, I. Post, L. Wei, Y. Zhang, K. Zhang, M. Bohr, A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications: Proc. Of International Solid State Circuits Conference, 2007, 324
[4]. Muhammad Khellah, Nam Sung Kim, Yibin Ye, Dinesh Somasekhar, Tanay Karnik, Nitin Borkar,Fatih Hamzaoglu, Tom Coan, Yih Wang, Kevin Zhang, Clair Webb, Vivek De ,VT-Variations and Supply-Noise Tolerant 45nm Dense Cache Arrays with Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits: Proc. Of 2008 IEEE Symposium on VLSI Circuits, 2008, 48-49
[5]. Baker Mohammad, Martin Saint-Laurent, Paul Bassett, Jacob Abraham , Cache Design for Low Power and High Yield: Proc. Of ISQED'08, 2008,103-107,

ABSTRACT:ThePaper Presents efficient implementation of downsampler and upsampler using Multirate digital signal processing system which includes sampling rate conversion. The adder which is used in down and upsampler is replaced by modified carry select adder and the circuit obtained is verified and compared successfully to show low power and area consumption and the same is implemented for tunable band pass filter A noised input speech signal is denoised after filtering in the multirate filter application. Reduction of power and area is important for VLSI system and also it becomes one of the most critical design parameter.
Keywords: VLSI-Very large scale integrated circuit, DSP-Digital signal processing, VHDL-Very high speed hardware description language, CSLA-Carry select adder, RCA- Ripple carry adder, BEC-Binary to excess 1 converter

[1]. An- YeuWut I, J. Ray Liu, Zhongying Zhang, Kazuo Nakajim,ArunRaghupathy"Low-Power Design Methodology for DSP Systems Using Multirate Approach".
[2]. Henry Samueli and Thu-ji Lin "A VLSI Architecture for aUniversal High-Speed Multirate FIR Digital Filter WithSelectable Power of Two decimation/Interpolation Ratios"
[3]. An-Yeu Wu, Member, IEEE, and K. J. Ray Liu, SeniorMember, IEEE "Algorithm-Based Low-Power TransformCoding Architectures: The Multirate Approach".
[4]. SayfeKiaei "Systematic Derivation of VLSI Arrays for DigitalDSP Algorithms".
[5]. O. J. Bedrij, "Carry-select adder," IRE Trans. Electron. Comput., pp. 340–344, 1962.
[6]. B. Ramkumar, H.M. Kittur, and P. M. Kannan, "ASIC implementation of modified faster carry save adder," Eur. J. Sci. Res., vol. 42, no.1, pp. 53–58, 2010.

ABSTRACT:parallal prefix adders are one of the fastest types of adder that had been created and developed. this paper investigates three types of carry-tree adders (the Kogge-Stone, sparse Kogge-Stone, and spanning tree adder) and compares them to the simple ripple carry adder and carry skip adder.these designs of varied bit widths were Implemented on a xilinx spartan 3E FPGA and delay measurements were made with a high performance logic analyzer .Due to the presence of a fast carry-chain,the RCA design exhibit better delay performance up to 128 bits.the carry tree adders are expected to have a speed advantage over the the RCA as bit widths approach 256.
Keywords: parallel prefix adder,Brent Kung adder, Kogge Stone adder, computational delay comparison, area comparison

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