iosr-JVSP   Volume-4 ~ Issue-4 ~ July-August 2014

ABSTRACT: Efficiency of adiabatic circuits is determined by the adiabatic and non-adiabatic losses incurred by them during the charging and recovery operations. Lesser be the losses more energy efficient would be the circuit. In this paper, a new approach i.e., Complementary Energy Path Adiabatic Logic (CEPAL), is presented to minimize power dissipation in quasi static energy recovery logic (QSERL). It optimizes circuit, by avoiding non-adiabatic losses completely by replacing the diodes with MOSFETs. MOSFET gates are controlled by power clocks and this is implemented in Carry Look-Ahead Adder structure. Firstly, the performance attributes of CEPAL Carry Look-Ahead Adder are compared against the conventional static CMOS logic counterpart to identify its adiabatic power advantage. The analyses are carried out using the industry standard Tanner EDA design environment using 250nm technology libraries. The results prove that CEPAL adiabatic Carry Look-Ahead Adder results in 56.05% of power savings over static CMOS.

Keywords: Carry Look-Ahead Adder; CEPAL (Complementary Energy Path Adiabatic Logic); Low Power; Power Clock; Ripple carry adder; Static adiabatic logic; Very Large Scale Integration (VLSI)

[1] David Harris, Neil H. E. Weste, Ayan Banerjee, CMOS VLSI Design-A Circuits and Systems Perspective, (Pearson Education, pp. 129-134).
[2] Samir S. Rofail, Kiat-Seng Yeo, Wang-Ling Goh, CMOS/BiCMOS ULSI: low voltage, low power, (Pearson Education, pp. 3-8, pp. 496-508).
[3] Y. Moon and D.-K. Jeong, An efficient charge recovery logic circuit, IEEE 1. Solid-State Circuits, vol. 31, no. 4, pp.514-522, Apr. 1996.
[4] Akramer, J.S.Denker, B.Flower, and J.Moroney, 2nd order adiabatic computation with 2N-2P AND 2N-2N2P logic circuits, Proc. Int. Workshop Low Power Design, Apr. 1995.
[5] Y.Ye and K.Roy, Energy recovery circuits using reversible and partially reversible logic, IEEE Trans. Circuits. Syst. I, vol. 43, pp 769-778, Sep. 1996.

ABSTRACT:In this paper, we present a method of detecting the splitting of heart sound S2 based on a template matching approach. A mathematical model of normal S2 is created and tested on other normal S2 complexes for goodness of fit. The generalized mathematical model is used as a template for detecting splitting of S2 sounds, as they will not generate a good fit with a model of a normal S2 complex. This automated detection of splitting of S2 can be used in the detection of congenital heart diseases or pulmonary hypertension. We have provided an estimate of the fit results of the mathematically synthesized S2 complex with the split S2 complexes.
Keywords: Curve fitting, Fourier Series, Goodness of fit, Phonocardiography, Splitting of S2.

[1] Howard B. Sprague, M.D., Patrick A. Ongley, M.D., "The Clinical Value of Phonocardiography", Circulation. 1954;9:127-134
[2] Sandra LachArlinghaus, PHB Practical Handbook of Curve Fitting. CRC Press, 1994.
[3] William M. Kolb. Curve Fitting for Programmable Calculators. Syntec, Incorporated, 1984
[4] Brooks, E.B.; Thomas, V.A; Wynne, R.H.; Coulston, J.W., "Fitting the Multitemporal Curve: A Fourier Series Approach to the Missing Data Problem in Remote Sensing Analysis," Geoscience and Remote Sensing, IEEE Transactions on , vol.50, no.9, pp.3340,3353, Sept. 2012,doi: 10.1109/TGRS.2012.2183137
[5] Brooks, E.B.; Thomas, V.A; Wynne, R.H.; Coulston, J.W., "Fitting the Multitemporal Curve: A Fourier Series Approach to the Missing Data Problem in Remote Sensing Analysis," Geoscience and Remote Sensing, IEEE Transactions on , vol.50, no.9, pp.3340,3353, Sept. 2012,doi: 10.1109/TGRS.2012.218313

ABSTRACT: Array multiplier occupies larger area so MBE is engaging approach to style efficient multiplier. This paper presents new concept which is able to optimize the realm and speed of information calculation. The modified Booth Encoder circuit generates half the partial products in parallel. By extending sign little bit of the operands and generating an extra partial product the SUMBE multiplier obtained. Parallel Prefix Adder wont to speed up the number operation. The new approach of 2'S complement has been introduced during this paper to cut back the realm of MBE.

Keywords: MBE, Radix 2n, Parallel Prefix adder, new approach of 2's Complement Method.

[1]. W. –C. Yeh and C. –W. Jen, "High Speed Booth encoded Parallel Multiplier Design," IEEE transactions on computers, vol. 49, no. 7, pp.692-701, July 2000.
[2]. Shiann-Rong Kuang, Jiun-Ping Wang, and Cang-Yuan Guo, "Modified Booth multipliers with a Regular Partial Product Array," IEEE Transactions on circuits and systems-II, vol 56, No 5, May 2009.
[3]. Li-Rong Wang, Shyh-Jye Jou and Chung-Len Lee, "A well-structured Modified Booth Multiplier Design" 978-1-4244-1617-2/08/$25.00 ©2008 IEEE.
[4]. Soojin Kim and Kyeongsoon Cho "Design of High-speed Modified Booth Multipliers Operating at GHz Ranges" World Academy of Science, Engineering and Technology 61 2010.
[5]. Magnus Sjalander and Per Larson-Edefors. "The Case for HPM-Based Baugh-Wooley Multipliers," halmers University of Technology, Sweden, March 2008.

ABSTRACT: Correct recognition of vehicles violating traffic rules and regulations is a major challenge in the present complex traffic environment. An automatic Number Plate Recognition (ANPR) system plays an important role in the detection of such events. In this paper, automatic number plate recognition (ANPR) was designed and implemented on Android mobile phone platform. First, the graphical user interface (GUI) for capturing image using built-in camera was developed to acquire car plate number. Second, the preprocessing of raw image was done using contrast enhancement, filtering, and straightening. Next, an optical character recognition (OCR) using neural network was utilized to extract texts and numbers. The proposed ANPR algorithm was implemented and simulated using Android SDK on a smart phone or PC. Future research includes optimizing the system for mobile phone implementation with limited CPU and memory resources, and geo-tagging of the image using GPS coordinates and online database for various mobile applications.

Keywords: ANPR, number plate, smart phone, android, image processing

[1]. Muhammad Tahir Qadri and Muhammad Asif, "Automatic Number Plate Recognition System for Vehicle Identification Using Optical Character Recognition", 2009 International Conference on Education Technology and Computer, pp. 335–338. 2009.
[2]. Neng-Sheng Pai, Sheng-Fu Huang, Ying-Piao Kuo1, Chao-Lin Kuo, "License Plate Recognition Based on Extension Theory," 2010 International Symposium on Computer, Communication, Control and Automation, pp. 164–167, IEEE 2010.
[3]. Thanongsak Sirithinaphong and Kosin Chamnongthai, "The Recognition of Car License Plate for Automatic Parking System", Fifth International Symposium on Signal Processing And its Applications, ISSPA '99, Brisbane, Australia, 22-25 August, 1999.
[4]. S. Thanongsak, and C. Kosin, 1998, "Extracting of Car License Plate Using Motor Vehicle Regulation and Character Pattern Recognition," Proceedings of the 1998 IEEE APCCAS '98 Asia-Pacific Conference on Circuit and Systems, pp. 559-562, November 24-27, 1998.
[5]. Sheng-Wen Chen, Chung-Huang Yang and Chien-Tsung Liu, "Design and Implementation Of Live SD Acquisition Tool in Android Smart Phone", 2011 Fifth International Conference on Genetic and Evolutionary Computing, pp. 157–162, IEEE Computer Society, 2011.

ABSTRACT: In recent years power consumption in CMOS VLSI circuits has become a major design constraint. This is in particular important for mobile wireless communication systems, due to the limited life time of the batteries to power wireless communication equipment. The circuit designers came with suitable low power strategies to achieve low power design. These circuit level techniques are readily available in the form of standard cells to the Register Transfer Level (RTL) designer. Currently designers are exploring the algorithm level and architecture level techniques towards arriving at low power communication Integrated Circuits (ICs). The Word Length Optimization (WLO) is an algorithmic approach with promising power saving levels, suitable for communication applications. The work presented here demonstrates power optimized RTL design for wireless base band receiver using Quadrature Phase Shift Keying (QPSK) modulation scheme. The novel method of arriving at suitable word lengths based on system level parameters at each signal stage is demonstrated. The Symbol Error Rates (SER) for given energy per symbol are analyzed. The Xilinx Zynq-7 Family FPGA is used for area, power and performance analysis. The peak power optimization of 40% is reported for Es/No = 8 dB, in comparison to the normal design.

Keywords: Base band receiver, Low power VLSI, Multiple word length optimizations, SNR degradation, Word Length Optimization

[1]. Walt Kester, "Taking the Mystery out of the Infamous Formula, "SNR = 6.02N + 1.76dB," and Why You Should Care", Analog Devices Tutorial, MT-001 Rev.A, 10/08, WK.
[2]. N. Alivelu Manga; M. Madhavi Latha, "An optimum ADC output word length selection for low power communication architectures," Advances in Computing, Communications and Informatics (ICACCI), 2013 International Conference on , vol., no., pp.569,574, 22-25 Aug. 2013, doi: 10.1109/ ICACCI.2013. 6637235.
[3]. Rekha Masanam (1), B.Ramarao, "Area Efficient Fft/Ifft Processor for Wireless Communication", IOSR Journal of VLSI and Signal Processing (IOSR-JVSP), Volume 4, Issue 3, Ver. III (May-Jun. 2014), PP 17-21.
[4]. Satyam Dwivedi, Bharadwaj Amrutur and Navakanta Bhat, "Power Scalable Radio Receiver Design Based on Signal and interference condition", Journal Low Power Electron. Appl. 2012, 2,242-264; doi:10.3390 / jlpea2040242, ISSN2079-9268
[5]. Nikita Patel, Satyajit Anand and P P Bhattacharya. Article: Design of Low Power Wake-up Receiver for Wireless Sensor Network. International Journal of Computer Applications 90(10):20-25, March 2014. Published by Foundation of Computer Science, New York, USA.

ABSTRACT: Dynamic threshold MOS (DTMOS) circuits provide low leakage and high current drive , compared to CMOS circuits, operated at lower voltages. This paper proposes a modified DTMOS approach called Variable threshold MOSFET (VTMOS) approach. The VTMOS is based on operating the MOS devices with an appropriate substrate bias, which varies with gate voltage by connecting a positive bias voltage between gate and substrate for NMOS and negative bias voltage between gate and substrate for PMOS. With VTMOS, there is considerable reduction in operating current and power dissipation, while the remaining characteristics are almost the same as those of DTMOS. Results of our investigations show that VTMOS circuits improves the power up to 50% when compared to CMOS and DTMOS circuits, in sub threshold- region. The performance characteristics of VTMOS shift register- The Power dissipation, Propagation delay and Power delay product have been evaluated through simulation using H spice. The dependency of these parameters on frequency of operation has also been investigated.

Keywords: Sub threshold, Dynamic threshold MOS Inverter, Propagation delay, Noise-margin ,Variable threshold MOS Inverter, Power dissipation.

[1]. H.Soeleman , K.Roy, and B.C.Paul. : "Robust Sub threshold Logic for Ultra Low Power Operation" ,IEEE trans VLSI system, Feb 2001,Vol. 9, PP. 90-99.
[2]. Jabulani: Nyathi and Brent Bero: "Logic Circuits Operating in Sub Threshold Voltages" , ISLPED 06, October 4-6, 2006, Tegernsee, Germany.
[3]. C.Hyung, - 11 Kim, H.Soeleman, and K.Roy: "Ultra-Low Power DLMS Adaptive Filter for Hearing Aid Applications" ,IEEE transactions on very large scale integration (VLS1) system, vol. 11, No.6, December, 2003. PP 1058-1067.
[4]. H. Soeleman and K. Roy,"Ultra-low power digital subthreshold logiccircuits", in Int. Symp. Low Power Electron. Design, 1999, pp. 94–96.
[5]. Fariborz Assaderaghi, Stephen Parke, Dennis Simitsky, Jeffrey Bokor, Ping K. KO. Chenming Hu:"A Dynamic Threshold Voltage MOSFET (DTMOS) for Very Low Voltage Opertaion" ,IEEE Electron device letters, vol. 13, No.12, December 1994.

ABSTRACT: A device core logic testing of analog signals with minimal area overhead for measuring on chip voltages in digital circuits can be adopted by built-in-self-test in a distributed architecture. Here for measuring this analog voltage, the subsampled signal pair is fed to delay measurement to measure the skew between this pair.The routing of analog signals over long paths can be minimized by using clock gating. A clock is routed serially to the nodes of analog test voltage with consists of delay cells, flipflops. However the test voltage to a scheme between pair of signals raise to the signal pair at node.

Index terms: built-in self-test (BIST), current starved, over-sampling ratio, quantization, subsamling.

[1] G. Banerjee, M. Behera, M. A. Zeidan, R. Chen, and K. Barnett, "Analog/RF built-in-self-test subsystem for a mobile broadcast video receiver in 65-nm CMOS," IEEE J. Solid-State Circuits, vol. 46, no. 9, 1998–2008, Sep. 2011.
[2] N. A. Mehta, G. V. Naik, and B. Amrutur, "In situ power monitoring scheme and its application in dynamic voltage and threshold scaling for digital CMOS integrated circuits," in Proc. ACM/IEEE Int. Symp. Low-Power Electron. Design, Aug. 2010, pp. 259–264.
[3] Y. Zheng and K. L. Shepard, "On-chip oscilloscopes for noninvasive time-domain measurement of waveforms in digital integrated circuits," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 11, no. 3,
pp. 336–344, Jun. 2003.
[4] R. Ho, B. Amrutur, K. Mai, B. Wilburn, T. Mori, and M. Horowitz, "Applications of on-chip samplers for test and measurement of inte-grated circuits," in Symp. VLSI Circuits Dig. Tech. Papers, 1998, 138–139.
[5] C.-L. Wey and S. Krishnan, "Built-in self-test (BIST) structure for analog circuit fault diagnosis," IEEE Trans. Instrum. Meas., vol. 39, no. 3, pp. 517–521, Jun. 1990

ABSTRACT: Micro-Electro-Mechanical Systems (MEMS) technology offers the opportunity to produce mechanical, electromechanical, and electrochemical devices with the same unprecedented levels of miniaturization, and functionality as modern Very Large Scale Integrated (VLSI). Micro grippers are used for manipulation of biological samples, for assembling of micro parts and for micro assembly. Electro thermal micro grippers are promising tools enabling assembly and manipulation of nano-scale structures. In this paper MEMS based U-shaped thermally actuated micro-gripper is designed using two hot and one cold arm type thermal actuator. Then the effect of coefficient of thermal expansion and poisson's ratio on stress for thermally actuated micro-gripper is analyzed and the results shows that the stress increases with the increase in coefficient of thermal expansion and the stress decreases with the increase in poisson's ratio.

Keywords: MEMS, Thermally Actuated Micro-gripper, Coefficient of Thermal Expansion, Poisson's Ratio

[1]. A. R. Kalaiarasi and Dr. S. HosiminThilagar, Design and Finite Element Analysis of Electrothermal Compliant Microactuators, Proc. ConfonCOMSOL, Bangalore, 2011.
[2]. ManpreetKaura and SandeepDhariwala, Parameters Affecting Electrothermal Actuation Based Microtweezers, IEEE Journal of Current Engineering and Technology, 2012, 305-309.
[3]. O. Sardan, D. H. Petersen, O. Sigmund and P. Bøggild, Simulation of Topology Optimized ElectrothermalMicrogrippers, Proc. ConfonCOMSOL, Hannover, Germany, 2008.

[4]. Lee, Sang H., Kwang-Cheol Lee, Seung S. Lee, and Hyeon-Seok Oh, Fabrication of an electrothermally actuated electrostatic microgripper, Proc. 12th International Conf. on Tansducers, Solid-State Sensors, Actuators and Microsystems,2003, 552-555.

[5]. Nordström Andersen, Karin, DirchHjorth Petersen, Kenneth Carlson, KristianMølhave, ÖzlemSardanSukas, Andy Horsewell, VolkmarEichhorn, SergejFatikow, and Peter Bøggild, Multimodal electrothermal silicon microgrippers for nanotube manipulation, IEEE Journal of Nanotechnology, 8, 2009, 76-85.

ABSTRACT: In this paper, different legalisation methods are examined for a new method of min-cut partitioning for VLSI placement. Traditional min-cut placers divide the given circuit into equal sized sub-circuits at each partitioning level. This paper uses a new partitioning method called unequal sized partitioning in which instead of making the sub-circuits size equal, the size of sub-circuits are made unequal. This paper analyses the placement results to minimize the total wire length of unequal sized partitioning for different legalisation schemes. Firstly an introduction to unequal sized recursive partitioning and legalisation schemes are presented. Then these schemes are applied to MCNC benchmark circuits for different partition ratios ranging from 0.1 to 0.9. The results prove that all the legalisation schemes do not give optimal wire lengths for equal sized partitioning. Each circuit has optimal wire length at different partition ratio for a different legalisation method. Finally this paper suggests the need for unequal sized partitioning which improves the wire length significantly as compared to the conventional equal sized partitioning.

Keywords: Legalisation, Min-cut algorithm, Partition ratio, Placement, Unequal sized partitioning

[1] Scott. Kirkpatrick, "Optimization by simulated annealing: Quantitative studies.," Journal of statistical physics 34.5-6 , pp. 975-986,
1984.
[2] Khushro, and Pinaki Mazumder. Shahookar, "VLSI cell placement techniques.," ACM Computing Surveys (CSUR) 23.2, pp. 143-
220, 1991.
[3] Maurice, and Jerome M. Kurtzberg. Hanan, "Placement techniques.," Design automation of digital systems 1, pp. 213-282, 1972.
[4] R-M., and Prithviraj Banerjee. Kling, "ESP: A new standard cell placement package using simulated evolution.," In Proceedings of
the 24th ACM/IEEE Design Automation Conference, pp. 60-66, 1987.
[5] Melvin A Breuer, "A class of min-cut placement algorithms," In Proceedings of the 14th Design Automation Conference, pp. pp.
284-290, 1977.