iosr-JVSP   Volume-4 ~ Issue-4 ~ July-August 2014

ABSTRACT: This paper presents a technique for enhancement of low contrast images using dynamic stochastic resonance(DSR) technique. Stochastic resonance is a technique in which noise signal is used to enhance the system performance. The noise can be added externally or internal noise of image can be used .However, in the proposed technique, internal noise is used for enhancement. Number of methods have been established for image enhancement but none of the methods used noise signal. In this paper, the performance of the proposed technique is also compared with the performance of the other existing techniques.

Keywords: Contrast enhancement, Non-linear system, Stochastic resonance

[1]. Zhuyou XI , Yunju YAN , Yu ZHANG, Liu LIU "Stochastic Resonance and its Application in Detecting Weak Signals‟ 2010 3rd International Congress on Image and Signal Processing (CISP2010)
[2]. Rajlaxmi Chouhan, Rajib Kumar Jha, Prabir Kumar Biswas : "Enhancement of Dark and Low-contrast Images using Dynamic Stochastic Resonance‟ , IET Image Process ., 2013, Vol. 7, Iss. 2, pp. 174–184
[3]. Benzi R，Sutera A, Vulpiani A. The mechanism of stochastic resonance. Journal of Physics A, Mathematical and General, 1981, pp.453~457.
[4]. L. Gammaitoni, P. Hanggi, P. Jung, and F. Marchesoni, "Stochastic resonance," Reviews of Modern Physics, vol. 70, pp. 223–270, 1998.
[5]. B. McNamara and K. Wiesenfeld, "Theory of stochastic resonance," Physical Review A, vol. 39, no. 9, pp. 4854–4869, 1989

ABSTRACT: This paper focuses on design of systolic architecture and by the application of evolutionary programming to achieve 100% HUE (Hardware Utilization Efficiency) for space representation containing delays in systolic design. Heuristic method involves EP (Evolutionary Programming) to solve the problems where the solution is in large search space. Using EP, we are able to find the number of different solutions for designing the systolic architecture for regular iterative algorithms. From which the user can choose any design of his choice according to his application.
Keywords: Systolic array architecture, Processing Element, Hardware Utilization Efficiency

[1]. G. S. Almasi and A. Gottlieb. Highly Parallel Computing Benjamin/Cummings, second edition, 1994
[2]. P.Banerjee. "Parallel Algorithmsfor VLSI Computer-Aided Design" Prentice-Hall, 1994.
[3]. R. Duncan. "Parallel computer architectures". In Advances in Computers, volume 34, pages 113-152. Academic Press, 1992.
[4]. VLSI Digital Signalling Processing Systolic Architecture Design-Lan- Da Van Phd. Dept.of Computer Science. National Chiao Tung University. Taiwan.R.O.C.Spring, 2007.
[5]. Evolutionary Programming:"Evolutionary and adaptive computing in Engineeering Design".-Ian.C.Parmee

ABSTRACT: This paper proposes a design to interface ADCs and DACs of different data width to a processor on an FPGA using VHDL. The ADCs and DACs are connected to a processor and the characteristics of the interface can be changed by programming the processor. Any generic device can be connected using the same interface. Verification is done by Open verification methodology using System Verilog.

Index Terms: ADC, DAC, IP core, FPGA, OVM testbench.

[1] H. Lei, "Design of embedded data acquisition system based on fpga," in Computer Science and Information Technology, 2009. ICCSIT 2009. 2nd IEEE International Conference on, Aug 2009, pp. 530–534.
[2] R. A. Bergamaschi and W. R. Lee, "Designing systems-on-chip using cores," in Proceedings of the 37th Annual Design Automation Conference, ser. DAC '00. New York, NY, USA: ACM, 2000, pp. 420–425. [Online]. Available: http://doi.acm.org/10.1145/337292.337526
[3] J. Weber and M. Chin, "Using fpgas with embedded processors for complete hardware and software systems," in Beam Instrumentation Workshop 2006(AIP Conference Proceedings Volume 868), vol. 868, 2006, pp. 187–192.
[4] S. Toscher, T. Reinemann, R. Kasper, and M. Hartmann, "A reconfigurable delta-sigma adc," in Industrial Electronics, 2006 IEEE International Symposium on, vol. 1, July 2006, pp. 495–499.
[5] C. Sisterna, M. Segura, M. Guzzo, G. Ensinck, and C. Gil, "Fpga implementation of an ultra-high speed adc interface," in Programmable Logic (SPL), 2011 VII Southern Conference on, April 2011, pp. 161–166.

ABSTRACT: Arithmetic circuit Multiplication happens oftentimes in finite impulse response (FIR) filters, quick Fourier transforms, distinct trigonometric function transforms, convolution, and to avoid wasting vital temporal order consumption of a VLSI style. Here, we have a tendency to propose planning of FIR filter exploitation high speed & space economical multiplier factor adopting the new implementing approach exploitation changed radix-4 booth multiplier factor. The multiplier factor is intended by a changed Booth formula that is controlled by a detection unit exploitation associate degree logic gate. The changed booth formula can scale back the amount of partial merchandise generated by an element of two.

Keywords: DSP, FIR Filter Design, Booth algorithm, Radix no. system, Xilinx tools, area, delay.

[1]. J.Douša, VHDL Language, Textbook CTU FEE 2003, in Czech
[2]. A.Pluha_ek, Computer Logic Design, Textbook CTU FEE 2003, in Czech
[3]. L.Ru_kay, Implementation of the IIR filter (Biquadratic Section) on the FPGA. Diploma
[4]. Thesis, CTU FEE Department of Circuit Theory, February 2005, in Czech
[5]. Richard S. Juszkiewicz, An Analysis of Interpolated Finite Impulse Response Filters
[6]. Their Improvements, IEEE Signal Processing Magazine, November 2005

ABSTRACT: A voltage regulator is a electronic circuit that maintains a constant output voltage irrespective of change in load current .With the rapid increase in circuit complexity and improved technology a more severe requirement for accurate and fast regulation is desired. This has led to need for new and more reliable design of buck converters. The buck converter inputs an unregulated dc voltage input and outputs a constant or regulated voltage. This paper discusses about efficient design of buck Converter with type 3 compensator and also gives detailed analysis on stability, steady state analysis, output ripple and Power efficiency. For investigating stability Mat-lab tool is used and system level simulation has been carried out with Cadence-P spice. With input voltage of 3 V and Output Voltage of 1.5V with variations in load current from 100mA-500mA, optimum efficiency of 93 % is obtained using 130nm CMOS Technology

Index Terms: Pwm,Mosfet,regulation, ripple

[1]. Bandyopadhyay S, Ramadass Y K, Chandrakasan A P. 20 uA to 100 mA DC–DC converter with 2.8–4.2 V battery supply for portable application. IEEE J Solid-State Circuits, 2011, 46(12): 2807
[2]. Huang H W, Chen K H, Kuo S Y. Dithering skip modulation,width and dead time controllers in highly efficient DC–DC converters for system-on-chip applications. IEEE J Solid-State Circuits, 2007, 42(11): 2451
[3]. Liou W R, Yeh M L, Kuo Y L. A high efficiency dual-mode buck converter IC for portable applications. IEEE Trans Power Electron,2008, 23(2): 667.
[4]. Jinwen Xiao, Angel Peterchev, Jianhui, Seth Sanders, "An Ultra-Low-Power Digitally-Controlled Buck Converter IC for Cellular Phone Applications", Applied Power Electronics Conference and Exposition, 2004. Nineteenth Annual IEEE, Volume 1, Issue, 2004 Page(s): 383 - 391 Vol.1
[5]. Chin Chang, "Robust Control of DC-DC Converters: The Buck Converter", Power Electronics Specialists Conference, 1995. 26th Annual IEEE Volume 2, Issue , 18-22 Jun 1995 Page(s):1094 - 1097 vol.2

ABSTRACT: This paper focuses on Analysis and experimental results of 6-bit charge-redistribution DAC and 6-bit charge-redistribution DAC using split array configuration. These DAC configurations are designed and simulated using GPDK 180nm CMOS technology. DAC is an important component within the SAR ADC. The charge redistribution DAC in a Split capacitor configuration has a total capacitance which is 87.5% smaller compared to a conventional design. Hence DAC gives the optimized architecture. Optimized design of DAC architecture ensures the accuracy of the components, which improves the performance of SAR ADC. The matching accuracy of integrated capacitors is excellent. The simulation results of both are compared. The delay required to get the output is 793.7E-15S and 793.6E-15S when all input bits are high for charge-redistribution DAC and split array DAC respectively. Dynamic range for these DACs is 35.98dB. The supply voltage is 1.8V.

Keywords: Analog- to- Digital converter, Digital- to- Analog converter, Charge redistribution, Successive Approximation, Split array.

[1]. PEI Xiaomin and ZHANG Jun, "Design and Optimization on the Interior DAC of SAR ADC", 2011 International Conference on Information Management and Engineering (ICIME 2011), IPCSIT vol. 52 (2012) © (2012) IACSIT Press, Singapore
[2]. Dariusz, Kościelnik, Marek, Miśkowicz, "Modeling event-driven successive charge redistribution in ADC with varying rate of charge transfer", 2012 IEEE 27th convention of Electrical and Electronics Engineers in Israel. Journal Papers
[3]. Olli Kursu and Timo Rahkonen, "Charge Scaling 10-bit Successive Approximation A to D Converter with Reduced Input Capacitance", 978-1-4577-05168/11/$26.00 @ 2011 IEEE.
[4]. Michiel van Elzakker, Member, IEEE, Ed van Tuijl, Member, IEEE, Paul Geraedts, Daniël Schinkel, Member, IEEE, Eric A. M. Klumperink, Senior Member, IEEE, and Bram Nauta, Fellow, IEEE, "A 10-bit Charge-Redistribution ADC Consuming 1.9 uW at 1 MS/s", IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 5, MAY 2010
[5]. [5] Phillip E. Allen and Douglas R. Holberg, "CMOS Analog Circuit Design", Second Edition, New York Oxford, Oxford University press 2004.

ABSTRACT: A multiband wireless system utilizes multiband frequencies in a single system for different wireless applications and the use of these systems is the most prominent feature of today's communication era. In spite of the complicated circuitry used to design these systems; these are widely used because of many important features and these systems are used with the help of timing and frequency control circuit which controls the frequency of the device according to the application. These circuits are used in mobile phones; laptops etc to provide them applications of different frequency range i.e. Bluetooth, WI-Fi, Zig-Bee and GPS etc. In this paper the timing and frequency control circuit is used in the form of PLL i.e. Phase Locked Loop. The PLL controls the frequency range of the circuit according to the application required and hence it can be used in multiband wireless systems. In this paper a timing and frequency control circuit is designed at system level, in which the center frequency is in GHz range and the reference frequency for the circuit is also in RF-range. By keeping the center frequency in GHz range, this PLL can be widely used in multiband wireless systems as it can easily adjust the frequencies required for particular applications. Each component is designed at system level using Verilog - A language in cadence with 1.8V power supply.

Keywords: Charge pump, Multiband wireless systems, PFD, PLL, VCO

[1]. C.S Vaucher "An Adaptive PLL Tuning System Architecture Combining High Spectral purity and fast settling time", IEEE Journal of Solid State Circuits, April 2000.
[2]. W.S.T Yan and H.C.Luong "A 2V 900 MHz Monolithic CMOS Dual-Loop Frequency synthesizer for GSM Receivers", IEEE Journal of Solid State Circuits, Feb 2001.
[3]. T.-C.Lee and B.Razavi "A Stabilization Technique for Phase locked Frequency Synthesizers", Dig. Symposium on VLSI circuits, June 2002.
[4]. John G. Maneatis, Jaeha Kim, Iain McClatchie, Jay Maxey and Manjusha Shankaradas"Self-Biased High-Bandwidth Low -Jitter 1-to-4096 Multiplier Clock Generator Pll", IEEE Journal of Solid State Circuits, VOL.38, N0.11, November 2003.
[5]. Thomas Olsson and Peter Nilsson"A Digitally Controlled PLL for SoC Applications",IEEE Journal of Solid State Circuits,VOL.39,N0.5,May 2004.

ABSTRACT: Concatenative speech synthesis using phoneme, di-phone and allophone as an elementary unit for Hindi speech synthesis requires significant quality improvement. The naturalness of the state of the art waveform synthesizer is attributed due to the use of syllable as a basic unit. The primary reason for choosing the syllable as a basic unit is that the Indian languages are syllable centered. This work proposes a syllable based speech unit for concatenative speech synthesis considering position of syllable in a word into account i.e the start, middle and end. This is achieved by building a standard syllable (C*V) level speech database consisting of 442 syllables in each position thus accounting for 1326 standard and non-standard words. Further the quality of synthesized speech is enhanced using moving average windowing. The effectiveness of the system is demonstrated by synthesizing natural sounding speech for Hindi, national language of India. An important advantage of this approach leads to reduced prosody mismatch and spectral discontinuity that occurs during syllable concatenation. The results obtained from the proposed system are far superior compared to the traditional unit based Text to Speech (TTS) synthesis system. The most important quality of this system is the improved naturalness in the synthesized speech.
Keywords: Concatenative synthesis, Hindi, Mean Opinion Score (MOS), Praat, TTS, UNICODE.

[1]. Thomas, Samuel, M. Nageshwara Rao, Hema A. Murthy, and C. S. Ramalingam. "Natural sounding TTS based on syllable-like
units." Energy 2, no. 4, 2006.
[2]. Sangamitra Mohanty, "Syllable Based Indian Language Text To Speech System",IJAET, Vol. I, Issue 2, 2011, pp. 138-143.

[3]. Pamela Chaudhury, Madhuri Rao and K Vinod Kumar, "Symbol Based Concatenation approach for Text to Speech System for
Hindi using Vowel classification technique", NaBIC 2009, pp. 1082-1087.
[4]. S P Kishore & Alan W Black, "Unit Size in Unit Selection Speech Synthesis", Indian Institute of Information Technology,
Hyderabad & ISRI Carnegie Mellon University. Eurospeech 2003

[5]. Ravi D J and Sudarshan Patilkulkarni, "A Novel Approach to Develop Speech Database for Kannada Text-to Speech System", Int.
J. on Recent Trends in Engineering & Technology, Vol. 05, No. 01, 2011.

ABSTRACT: A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by either the customer or a designer after manufacturing – hence "field-programmable". In-flight reconfigurability and dynamic partial reconfiguration enhances space applications with re-programmable hardware and at run-time adaptive functionality attracts the use of FPGAs. FPGAs can provide designers with almost limitless flexibility, but once FPGA is programmed and interfaced with other pheripherals, it's difficult to change the application which is running on FPGA. So, here we use a wireless programming technique to configure the FPGA based on our requirement. A wireless medium is preferred so as to avoid a physical connection with FPGA. In our idea we are going to select the application program in RAM and directly configuring it to FPGA using GSM. Hence we can swap from one application program to another by using a message sent from the user.

Keywords: Arduino, AVR, FPGA, GSM

[1]. Guifen Gu and Guili Peng, The survey of GSM wireless communication system 2010 International conference on computer and information application (ICCIA)
[2]. Malik U and Diessel O, On the placement and granularity of FPGA configurations 2004 IEEE International conference on Field- Programmable technology
[3]. Steven F.Barrett, Arduino Microcontroller Processing for Everyone (Morgan and Claypool publications 2010)
[4]. Lawal N, Thomberg B and O'Nils M, Architecture driven memory allocation for FPGA based real-time video processing systems
[5]. 2011 VII Southern Conference on Programmable logic (SPL)
[6]. Dehng G.K, Kuo C.F and Wang S.T, A single-chip RF transceiver for quad-band GSM/GPRS applications 2004 IEEE Radio frequency integrated circuits (RFIC) Symposium