iosr-JVSP   Volume-4 ~ Issue-5 ~ Sep-Oct 2014

ABSTRACT: This paper describes an Underwater Acoustic Communication system for establishing a two-way communication between monitoring station and the underwater device. In order to obtain high data rates with utilization of an effective bandwidth, Orthogonal Frequency Division Multiplexing Technique (OFDM) has been chosen. With the proposed OFDM parameters, we have done an offline analysis of the data and had even verified the results using an existing modem.

Keywords: OFDM; FFT; FPGA; QPSK; SDR; ISI.

[1] Walter Tuttlebee, "Software Defined Radio: Baseband Technologies for 3G Handsets and Basestations", John Wiley & Sons Ltd-2004 Edition.

[2] FFT v8.0 IP core from www.xilinx.com.

[3] Shengli Zhou, Zhaohui Wang, "OFDM for Underwater Acoustic Communications",Wiley Edition.

[4] Yong Soo Cho, Jaekwon Kim,Won Young Yang, Chung G. Kang "MIMO-OFDM Wireless communications with MATLAB" John Wiley & Sons (Asia) Pte Ltd-2010 Edition.

[5] Rulph Chassaing, "Digital Signal Processing and Applications with the C6713 and C6416 DSK", Wiley Edition

ABSTRACT: In this paper VLSI layout designing and optimization techniques for different full adder topologies like Complementary MOSFET full adder (CMOS),Transmission gate full adder(TGA),Complementary Pass transistor Logic full adder(CPL) and Domino Full Adder has been discussed. Power consumption and propagation delay are the major issue for low voltage level circuit application designing in recent years. Full adders are the very important circuit element for calculating the basic four mathematical operations (addition, subtraction, multiplication and division) functions in Integrated circuits. In VLSI systems such as microprocessors and application specific DSP architecture are using different full adders for calculating mathematical operations. In this paper one bit full adders topologies has been used for analysis. The layout designing of the basic logic gates and different full adders is done using L-Edit v14.11 Tanner EDA tool using 0.18μm technology node. The results shows that parameters like Power consumption and total propagation delay, for a particular aspect ratio the Transmission Gate Full adder consume less power and having less propagation delay. Keywords: CMOS full Adder, CPL full adder, layout designing, Domino Logic Full adder, L-Edit v14.11 Tanner EDA tool, Transmission Gate Full adder.

[1]. Dan Clein and Gregg Shimokura CMOS IC Layout: Concepts, Methodologies and Tools, Newnes ,pp 22-40,(2000).

[2]. Sung-Mo Kang and Yusuf Leblebici, CMOS Digital Integrated Circuits: Analysis and Design, TATA McGraw Hill, Third Edition, pp 66-67, (2003).

[3]. John P. Uyemura, Chip Design for Submicron VLSI: CMOS Layout and Simulation, CENGAGE Learning, pp 36-37,(2006).

[4]. Mahnoush Ruholamini, Amir Sahafi, Shima Mehrabi and Nooshin Dadkhahi,Low-Power and High-Performance 1-Bit CMOS Full-Adder Cell, Journal of Computers, Vol. 3, No. 2, , (2008), pp. 48-54.

[5]. Reto Zimmermann and Wolfgang Fichtner, Low-Power Logic Styles: CMOS Versus Pass-Transistor Logic, IEEE Journal of Solid-State Circuits, Vol. 32, No. 7, (1997), pp. 1-12.

[6]. Vahid Foroutan, Keivan Navi and Majid Haghparast, A New Low Power Dynamic Full Adder Cell Based on Majority Function, World Applied Sciences Journal, Vol. 4, No.1,(2008), pp. 133-141.

ABSTRACT: The aim of this paper is to present the BIST architecture of generic multipliers. The generic architecture of all the four multipliers i.e. array, column bypass, wallace tree and booth multiplier has been designed .The verification of all these four different multipliers has been done by using BIST controller.The LFSR (linear feedback shift register) has been designed, which will generate the automatic inputs.Then the BIST controller has been designed which will check these multipliers by using input patterns obtained from LFSR. BIST controller will verify these four generic architectures whether they are faulty or not By using it, the logics or design of these multipliers need not to be verified by any other means.This is the advantage of this design that it does not require third party verification.The simulation has been carried out on ModelSim (Student Editon) EDA tool 10.0c and synthesis has been carried out on ISE Design Suite 14.4.

Keywords: Array Multiplier, BIST, Booth Multiplier, Column Bypass Multiplier, Wallace tree Multiplier

[1]. N.Ravi, Dr.T.S.Rao, Dr.T.J.Prasad."Performance Evaluation of Bypassing Array Multiplier with Optimized Design", International Journal Of Computer Applications (0975-8887), Vol28 No.5, 3 (2011).
[2]. Mahzad Azarmehr., "Multipliers, Algorithm And Hardware Designs", Research Center for Integrated Microsystem, 10 (2008).
[3]. Nishat Bano, "VLSI Design of low power booth multiplier", International Journal of Scientific and Engineering Research Vol 3 issue 2, 1-2(feb-2012).
[4]. C.Krishnamacharya ,CH. Sravanthi, K. Avinash, K.V. Uma Maheswaar Rao.,"Design of low power 2-D Multiplier using Bypassing Technique",International Journal of Innovative Research and Studies ISSN-2319-9725, 198 (May 2013).
[5]. Partha Sarathi Mohanty, "Design and Implementation of low power multipliers" WILLOW project, 16, 26 (2009).

ABSTRACT: This paper describes a design and implementation of bist technique in uart serial communication. Asynchronous serial communication is usually implemented by uart which is mostly used for less distance, low speed, low cost data to exchange between processor and peripherals. But due to the errors produced in the output of the data received the circuits are being not performed well in the functions In order to reduce the possibility of product failures and missed market opportunities by providing the need to ensure the data to be transferred in error proof.

[1]. Chakrabartyl,"Deterministic Built-in Test Pattern Generation for High-Performance Circuits Using Twisted-Ring Counters," IEEE Trans. of VLSI Systems, Vol. 8, No. 5, pp. 633636, Oct. 2000
[2]. Naresh, Vatsalkumar and Vikaskumar Patel, "VHDL Implementation of UART with Status Register", in the proceedings of International Conference on Communication Systems and Network Technologies, IEEE Computer Society, 11-13th May 2012, DOI: 10.1109/CSNT.2012.164, pp.750-754.
[3]. Fang Yi-yuan and Chen Xue-jun, "Design and Simulation of UART Serial Communication Module Based on VHDL", in the proceedings of 3rd International Workshop on Intelligent Systems and Applications (ISA), IEEE, May 2011, DOI 10.1109/ISA.2011.5873448, pp.1-4.
[4]. S. R. Das, "Built-in self-testing of VLSI circuits," IEEE Potentials, vol.10, pp. 23–26, Oct. 1991.
[5]. Dr. T.V.S.P.Gupta, Y. Kumari and M. Ashok Kumar, "UART realization with BIST architecture using VHDL", in the proceedings of International Journal of Engineering Research and Applications, February 2013, Vol. 3, Issue 1, ISSN: 2248-9622, pp.636-640.

ABSTRACT: In this paper, low power built-in self test (BIST) is implemented for 32 bit Vedic multiplier. The objective of this work is to reduce power dissipation in BIST with increased fault coverage. Various methods of pattern generation are compared keeping in view of power consumption. In this test pattern generation the seed value is changed every 2m clock cycles. For this purpose m bit binary counter and gray code generator is used. Signature analysis is done with the help of Multiple input signature register (MISR). The signature of MISR will indicate whether the circuit under test (CUT) i.e Vedic Multiplier is faulty or not. The results are tabulated and compared. From the implementation results, the low power BIST shows better power reduction than other methods. Simulation is carried out in Xilinx ISE and the design is implemented using vertex 5 field programmable gate array (FPGA).

[1]. Chakrabarty, et. al, "Deterministic Built-in Test Pattern Generation for High Performance Circuits Using Twisted-Ring Counters," IEEE Trans. of VLSI system, Vol. 8, No.5, pp. 633-636, Oct 2000.
[2]. Hakmi A. W , "Programmable deterministic built-in self test", IEEE international Test Conference OAI (ITC), Nov 2007.
[3]. Katti R.S , Ruan X.Y, and Khattri.H , "Multiple Output Low-Power Linear Feedback Shift Register Design,"IEEE Trans.circuits & Systems .I,Vol.53,No.7,pp-1487- 1495,July 2006.
[4]. Mechrdad Nourani, "Low-transition test pattern generation for BIST-based applications", IEEE transactions onComputers, Vol 57, No.3,2008.
[5]. Miron Abramovici, "Design for testability", revised edition, Nov 1997.

ABSTRACT: In this thesis, we address the interconnect problem in the deep sub-micron (DSM) regime. In VLSI interconnects to restore the input signal affected by the parasitic buffers are placed in between interconnects. But buffers has a certain switching time that contribute the overall signal delay and crosstalk delay. The designs of sized logic and repeater insertion for improved delay, power and placement are implemented by using both Schmitt trigger and buffer insertion. In this work replacement of sized logic with buffers with Schmitt trigger based on sizing is proposed for the signal restoration and to reduce delay. Because of adjustable threshold voltage Vth of Schmitt trigger the delay and power can be reduced in interconnects when compared to buffers. HSPICE simulations are carried out for the different PTM based on sized logic shows that Schmitt trigger with sized logic gives 12.45 % less delay when compared to buffer sized logic and also average power reduced to 5.09 % in case of Schmitt trigger when compared to sized logic of buffer. Keywords: Delay, DSM, Interconnects, power , Repeater, Schmitt trigger, sized logic.

[1] H.Bakoglu "Circuits, Interconnections and Packaging for VLSI" Addison-Wesley publishing company 1990.

[2] J. M. Rabaey "Digital Integrated Circuits a Design Perspective" Englewood Cliffs NJ: Prentice-Hall 1996.

[3] Yehea I. Ismail and Eby G. Friedman "Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits" IEEE Transaction on very large scale integration Systems, VOL. 8 NO. 2, April 2000.

[4] S. Dhar and M. A. Franklin, "Optimum buffer circuits for driving long uniform lines" IEEE J. Solid-State Circuits, vol. 26 no. 1, pp. 33-38 Jan. 1991.

[5] J. Cong, L. He, C.-K. Koh, and P. Madden "Performance optimization of VLSI interconnect" Integration, vol. 21, pp. 1-94 Nov. 1996

ABSTRACT: Change detection of the satellite images based on the contourlet image fusion and reformulated fuzzy clustering for change detection.Here the image fusion is used to produce difference image from log ratio and mean ratio imagesFor an optimal difference image,it should retain the unchanged areas and enhance the changed areas.So contourlet based image fusion is proposed to generate the difference images.This difference image should preserve the curves so that the clarity of the image become more.The method of differencing images from the log ratio and mean ratio of the individual images.The difference image have better quality.To process the difference image is to discriminate changed regions from the unchanged regions using reformulated fuzzy local information c means algorithm which is insensitive to noise.Experiment result shows that this approach provide better performance than its preexistence. Verified the proposed fusion algorithm and clustering algorithm by well -known image fusion measures and calculate the percentage correct classification.On the basis of experimental results it was found that performances of the proposed fusion method and clustering methods are better than the preexisting one.
Keywords: Contoulettransform,Image fusion ,Reformulated fuzzy clustering,change detection

[1] MaoguoGong,MemberIEEE,zhiqiangzhou,andjingjingMa,"Change detection in synthetic aperture radar based on image fusion and fuzzy clustering," April 2012.

[2] MerinAyshuAli,DR.B.M.Imran,"Change detection in SAR image using contourlet," International journal of scientific and engineering research volume 4,August 2013.

[3] PalleE.T.Jorgensen and Myung-sin song, "Comparison of discrete and continuos wavelet transforms," , Mar. 2010

[4] Yakoubbazi,Lorenzobruzzone,faridmelgani, "Image thresholding based on the EM algorithm and the generalized gaussian distribution,"epartment of information and communication technologies,university of Trento,via sommarive,14,I-38050,Trento,italy, May. 2006

[5] C.K Leung and F.K Lam, "Performance analysis for aclass of iterative imagethresholding algorithms ," Department of electronics engineering,Thehongkongpolytechinicuniversity,hong kong,Depratment of electrical and electronics engineering,,the university ofhongkong,hongkong, january. 1996..

ABSTRACT: The choice of flip-flop technologies is an essential importance in design of VLSI integrated circuits for high speed and high performance CMOS circuits. The main objective of the papert is to design a Low-Power Pulse-Triggered flip-flop. Flip-flops are the major storage elements in all SOC's of digital design. They accommodate most of the power that has been applied to the chip. Flip-flop is one of the most power consumption components. It is important to reduce the power dissipation in both clock distribution networks and flip-flops. The proposed low-power implicit-type P-FF design features a conditional pulse-enhancement scheme. First, the pulse generation control logic, an AND function, is removed from the critical path to facilitate a faster discharge operation. A simple two-transistor AND gate design is used to reduce the circuit complexity. Second, a conditional pulse-enhancement technique is devised to speed up the discharge along the critical path only when needed. As a result, transistor sizes in delay inverter and pulse-generation circuit can be reduced for power saving. Low power 4-bit shift registers are implemented using the proposed low power pulse triggered flip-flop with conditional pulse enhancement scheme.

Keywords: IP-DCO, MHLFF,SCCER, SISO, SIPO, PIPO, PISO.

[1] Hamada.M, Fujita.T, Hara.H, Ikumi.N, and Oowaki.Y, "Conditional data mapping flip flops for low-power and high-performance systems," IEEE Transactions on Very Large Scale Integrated (VLSI) Systems, 2006,December,vol. 14, pp. 1379–1383.

[2] Kawaguchi.H and Sakurai.T, "A reduced clock-swing flip-flop (RCSFF) for 63% power reduction," IEEE J. Solid-State Circuits, vol. 33, no. 5, pp. 807–811

[3] Klass.F, Amir.C, Das.A, Aingaran.K, Truong.C, Wang.R, Mehta.A,Heald.R, and G.Yee, "A newfamily of semi-dynamic and dynamic flip flops with embedded logic for high-performance processors," IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 712–716.

[4] Kong.B, Kim.S, and Jun.Y, "Conditional-capture flip-flop for statistical power reduction," IEEE J. Solid-State Circuits, Aug. 2001 vol. 36, no. 8, pp.1263–1271.

[5] Mahmoodi.H, Tirumalashetty.V, Cooke.M, and Roy.K, "Ultra low power clocking scheme using energy recovery and clock gating," IEEE Transactions on Very Large Scale Integrated (VLSI) Systems, Jan. 2009,vol. 17, pp. 33–44.

ABSTRACT: Advanced Encryption Standard (AES) a National Institute of Standards and Technology specification is an approved cryptographic algorithm that can be used for securing electronic data. Reprogrammable devices such as Field Programmable Gate Arrays (FPGA) are highly attractive option for hardware implementations of cryptographic algorithm AES as they offer a quicker and more customizable solution. This paper proposes an efficient FPGA implementation of advanced encryption standard (AES). We implement the AES encryption algorithm on Xilinx Spartan-3 FPGA and decryption is done on PC. The coding for encryption is done in VHDL language and for decryption in Visual Basic. To implement AES Rijndael algorithm on FPGA plain text of 128 bit data is considered. Advanced Encryption Standard (AES) RIJNDAEL on FPGA offers a better performance than any other cryptographic algorithms. Keywords: AES Rijndael algorithm, Decryption, Encryption, FPGA.

[1] Hamdan.O.Alanazi, B.B.Zaidan, A.A.Zaidan, Hamid A.Jalab, M.Shabbir and Y. Al-Nabhani, "New Comparative Study between DES, 3DES and AES within Nine Factors", Journal of Computing, Volume 2, Issue 3, March 2010, ISSN 2151-9617
[2] A.A.Zaidan, B.B.Zaidan, Anas Majeed, "High Securing Cover-File of Hidden Data Using Statistical Technique and AES Encryption Algorithm", World Academy of Science Engineering and Technology (WASET), Vol.54, ISSN: 2070-3724, P.P 468-479.
[3] National Institute of Standards and Technology, Advanced Encryption Standard (AES), Federal Information Processing Standards Publications – FIPS 197
[4] J. Daemen and V. Rijmen, AES submission document on Rijndael, Version 2, September 1999.(http://csrc.nist.gov/ CryptoToolkit/aes/rijndael/Rijndael.pdf)
[5] Leelavathi.G, Prakasha.S, Shaila.K, Venugopal K.R, L M Patnaik," Design and Implementation of Advanced Encryption Algorithm with FPGA and ASIC", IJREAT International Journal of Research in Engineering & Advanced Technology, Volume 1, Issue 3, June-July, 2013

ABSTRACT: Gate Diffusion Input (GDI) is a technique for designing low power circuits. This technique allows usage of less number of transistors as compared to CMOS logic. The basic GDI cell consists of only two transistors which are used to implement the basic logic functions. Because of less number of transistors, the switching is reduced and hence there will be a less power, delay and also reduced area. Complex functions can also be implemented using this technique. In this paper basic GDI cell is modified to get a "good" logic 0 and it is compared with the CMOS logic. The low power full adder is designed using GDI technique and is modified to get the strong logic zero. Using this modified GDI full adder, 4 bit Ripple Carry Adder and 4*4 Array Multiplier are designed and simulated. The simulation is done using CADENCE VIRTUOSO based on 45nm technology with the supply voltage of 1.2V.
Keywords: Full Adder, Ripple Carry Adder, Multiplier, Low Power, GDI.

[1]. Gary Yeap, " Practical Low Power Digital VLSI Design", Kluwer Academic Publishers.
[2]. Arkadiy Morgenshtein, Alexander Fish & Israel A Waganer, "Gate Diffusion Input ( GDI): A power efficient method for Digital Combinational circuits", IEEE Transactions on VLSI Systems, Vol 10, No.5, Oct 2002.
[3]. Madhusudhan Dangeti1 , S.N.Singh2, " Minimization of Transistors Count and Power in an Embedded System using GDI Technique : A realization with digital circuits", International Journal of Electronics and Electrical Engineering ISSN : 2277-7040 Volume 2 Issue 9 (September 2012)
[4]. Jayram Shrivas, Shyam Akashe, Nitesh Tiwari, "Design and Performance Analysis of 1 bit Full Adder using GDI Technique in Nanometer Era",
[5]. Po-Ming Lee, Chia-Hao Hsu, and Yun-Hsiun Hung," Novel 10-T full adders realized by GDI structure" 2007 IEEE International Symposium on Integrated Circuits (ISIC-2007).