iosr-JVSP   Volume-6 ~ Issue-6 ~ Nov-Dec 2016

ABSTRACT: Wavelet based hierarchical image compression algorithms, used to omit unnoticeable details of the image at the receiver by decomposing the image into bands i.e., low band image is coded with high bits and high band image is coded with low or desired bits, encoded with the codec data rate on a communication channel and the reconstructed image is compared with the compressed image for its accuracy, have become rich in reconstruction of vast amount of degraded image under several types of artifact and to improve transmission and storage capability

Keywords: Data rate, Image Codec, Image Compression, Image Wavelet, Hierarchical Tree

[1]. J.M. Shapiro, ―Embedded image coding using the zero trees of wavelet coefficients‖, IEEE Transactions on Image Processing, Vol. 41, No. 12, pp. 3445-3462, December 1993.
[2]. Amir Said, and Pearlman, W. A., "A New, Fast, and Efficient Image Codec Based on Set Partitioning in Hierarchical Trees" , IEEE
Trans. Circuit and systems for Video Technology, vol. 6, no. 3, pp. 243-250, June 1996.
[3]. J. S. Walker and T. Q. Nguyen, ―Wavelet-Based Image Compression,‖ Ch. 6 in The Transform and Data Compression Handbook, edited by K. R. Rao and P. C. Yip, CRC Press, 2001.
[4]. S.Jagadeesh, Dr. E. Nagabhooshanam, "Embedded Zero Binary Tree Wavelet Based SPIHT" in National Conference on
Communications, Signal Processing & Systems (NCCSPS - 2014) during 24- 25, August 2014, conducted by Department of ECE,
JNTUH College of Engineering, Hyderabad.

ABSTRACT: The modified algorithm has made multiplication easy. The algorithm consists of recoding table; it is used to minimize the partial products of the multiplier. We introduced an optimized design of add multiply operator which is based on a single data path. In this three different techniques are introduced (SMB1, SMB2, and SMB3) for the even and odd bit. Modified booth algorithm is mainly used to reduce the number of partial products. This design is used to achieve high performance and to improve the accuracy, reduction in power consumption and critical area. The recoding technique implementations and comparison has done with existing and designed modified booth recoder.

[1]. A. Amaricai, M. Vladutiu, and O. Boncalo, "Design issues and implementations for floating-point divide-add fused," IEEE Trans. CircuitsSyst. II–Exp. Briefs, vol. 57, no. 4, pp. 295–299, Apr. 2010.
[2]. E. E. Swartzlander and H. H. M. Saleh, "FFT implementation with fused floating-point operations," IEEE Trans. Comput., vol. 61, no. 2, pp. 284–288, Feb. 2012.
[3]. S. Nikolaidis, E. Karaolis, and E. D. Kyriakis-Bitzaros, "Estimation of signal transition activity in FIR filters implemented by a MAC architecture," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol.19, no. 1, pp. 164–169, Jan. 2000.
[4]. Y.-H. Seo and D.-W. Kim, "A new VLSI architecture of parallel multiplier–accumulator based on Radix-2 modified Booth algorithm,"IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol.
[5]. no. 2, pp. 201–208, Feb. 2010.W.-C. Yeh and C.-W. Jen, "High-speed and low-power split-radix FFT," IEEE Trans. Signal Process., vol. 51, no. 3, pp. 864–874, Mar. 2003.

ABSTRACT: Multiplier-less FIR filter design is the major requirement in VLSI signal processing. In this work the practical FIR low pass filter is designed using hybrid window for various mathematical operations like addition, average, exclusive-or and multiplication. Their frequency responses are obtainedby using Matlab. Multiplication based design of FIR Low Pass Filter (LPF) is realized in direct form structure and implemented in VLSI. This structure consists of adders, multipliers and delay elements..........

Keywords: CSD algorithm,Double precision format, FIR filter, Hybrid window,Q format

[1]. Eppili Jaya, K.ChitambaraRao, JayalaxmiAnem "FIR filter design using new Hybrid Window functions", IJSETR, Vol.4 Issue 6, JUNE – 2015, ISSN: 2278-7798.
[2]. Eppili Jaya, K.ChitambaraRao "Power, Area and Delay Comparision of Different Multipliers". IJSETR, Volume 5, Issue 6, June 2016, ISSN: 2278-7798.
[3]. Muralidhar, P. V., Nataraj, D., LokeshRaju, V., &Naik, S. K. (2010, July). Implementation of different FIR high pass filters using fractional Kaiser window. In Signal Processing Systems (ICSPS), 2010 2nd International Conference on (Vol. 2, pp. V2-651). IEEE.
[4]. Muralidhar, P. V., AS SrinivasaRao, and S. K. Nayak. "Spectral Interpretation of Sinusoidal Wave using Fractional Fourier Transform Based FIR window Functions." International Review on Computers and Software 4.6 (2009): 652-657.

ABSTRACT: With the extent of video coding applications in various domains, the need for faster and reliable modelling of video codec's is in raise. The conventional modelling of video codec's were developed for high resource compatibility. As the applications of video coding has moved to low resource devices, a need for the proposal of new coding, streaming and buffering logic in resource constraint environment is required. In this paper an approach for the modelling of video coding process using............

Keywords: Video codec; coding; steaming; buffering unit; codec modelling.

[1] Kristof Denolf, Adrian Chirila-Rus, Paul Schumacher, Robert Turney, Kees Vissers, Diederik Verkest, and Henk Corporaal, "A Systematic Approach to Design Low-Power Video Codec Cores", EURASIP Journal on Embedded Systems Volume 2007.

[2] Paul Schumacher, Wilson Chung, "FPGA-Based MPEG-4 Codec", DSP magazine, October 2005.

[3] Y. Zhang, W. Gao, Y. Lu, Q. Huang, and D. Zhao, "Joint source channel rate-distortion optimization for H.264 video coding over error prone networks," IEEE Trans. Multimedia, vol. 9, no. 3, pp. 445–454, Apr. 2007.

[4] Z. Chen, M. Li and Y.-P. Tan, "Perception-aware multiple scalable video streaming over WLANs," IEEE Signal Processing Letters, vol. 17, no. 7, pp. 675-678, July 2010.

[5] A. Argyriou, "Cross-layer adaptive ARQ for uplink video streaming in tandem wireless/wireline networks," in Proc. IEEE Multimedia Signal Processing Workshop (MMSP), Oct. 2007.

ABSTRACT: The purpose of the paper is to design the shifter by using different asynchronous logics to optimize the power dissipation and better performance. Power dissipation is a most important consideration as performance and area of Very Large Scale Integration (VLSI) design. The shifter in a digital circuit is frequently utilized by embedded digital signal processors and ALU of microprocessors to manipulate data. This paper explores design for the shifter to perform 1-bit right shift operation. The architecture of shifter is designed by a sequence of multiplexers (2:1 MUX) and in such an implementation the output of a MUX is connected to the input of the next MUX. The shifter was implemented in two different clock-less logics which are Multi-Threshold Null Conventional Logic..........

Keywords: Intermediate product shifter, clockless logic, 2:1 MUX, dual spacer, dual rail.

[1]. Kiat Seng Yeo, Kaushik Roy, Low Voltage, Low Power VLSI Subsystems, Tata McGraw Hill, 2005.
[2]. J. Sudhakar, A. Mallikarjuna Prasad, Ajit Kumar Panda, "Multi-Objective analysis of NCL threshold gates with Return to zero protocols," IOSR Journal of Electronics and Communication Engineering (IOSR-JECE), Vol 10, issue 3, Ver. II (May- Jun 2015), PP12-17.
[3]. Andrew Bailey, Ahmad Al Zahrani, Guoyuan Fu, Jia Di, Scott Smith, Multi-Threshold Synchronous Circuit Design for Ultra-Low Power, Journal of Low Power Electronics, Vol.4, 1–12, 2008.
[4]. Weste Neil H.E. and M. David Harris, CMOS VLSI Design: A Circuits and Systems Perspective, Fourth Edition. Boston: Pearson/Addison-Wesley, (2010).
[5]. D. J. Kinniment, "An evaluation of asynchronous addition", IEEE transaction on very large scale integration (VLSI) systems, vol.4, pp.137-140, March 1996.

ABSTRACT: The face recognition is used to identify a person for access into work place, home, electronic gadgets etc. In this paper, we propose Reversible Logic MUX-Multiplier (RLMM) based Face Recognition using Hybrid Features. The novel concept of RLMM is introduced in designing multiplier for edge detection of face images using reversible logic gates. The steganography is used to convert two images of same person into one image. By using Canny Edge Detection, the edge detected stegoimages are obtained in order to create the database. The resize and Gaussian filter techniques are used in preprocessing of face images. The Discrete Wavelet Transform (DWT) and Local Binary Pattern (LBP) coefficients are computed from images and are fused to extract initial features...........

Keywords: Biometrics, Canny Edge Detection, DWT, Face recognition, LBP, Steganography

[1] Himanshu Thapliyal and M.B Srinivas, "Novel Reversible Multiplier Architecture Using Reversible TSG Gate", IEEE International Conference on Computer Systems and Applications, pp.100 - 103, 2006.
[2] Nidhi Pokhriyal, Harsimranjit Kaur and Neelam Rup Prakash, "Compressor Based Area-Efficient Low-Power 8x8 Vedic Multiplier", International Journal of Engineering Research and Applications, Vol. 3, Issue 6, pp.1469-1472, 2013.

[3] Maryam Ehsanpour, Payman Moallem and Abbas Vafaei, "Design of a Novel Reversible Multiplier Circuit using Modified Full Adder", IEEE International Conference on Computer Design and Applications, Vol. 3, pp. 230-234, 2010.

[4] Madhusmita Mahapatro, Sisira Kanta Panda, Jagannath Satpathy, Meraj Saheel , M.Suresh, Ajit Kumar Panda and M K Sukla, "Design of Arithmetic Circuits Using Reversible Logic Gates and Power Dissipation Calculation" International Symposium on Electronic System Design, pp. 85 - 90, 2010.

[5] Anindita Banerjee and Anirban Pathak, "Reversible Multiplier Circuit" Third International Conference on Emerging Trends in Engineering and Technology. pp.781-786, 2010.

ABSTRACT: The simultaneous reception and transmission of the data in parallel communication is cost effective and the complexity for the system resources increases. To overcome such drawback and to perform an effective transmission/reception, the serial communication protocols were came into existence. Universal Asynchronous Receiver and Transmitter (UART) is a kind of serial communication protocol. Transmission and reception techniques are discussed and analysed for reliable data transmission

Keywords: UART, Transmitter, Receiver,ModelSim_Altera;

[1] Hu Hua, BAI, feng-e. Design and simulation of UART serial communication module based on Verilog –HDL [J]. J ISUANJ I YU XIANDA IHUA 2008 VOL.8 Frank Durda Serial and UARTTutorial.
[2] R. J. Samuel, Self-tuning baud rate generator for UART applications, USA: 7062003B2, 2006.
[3] Amanpreet kaur, Amandeep kaur, an approach for designing a universal asynchronous receiver transmitter "UART". International Journal of engineering research and application(IJCERA)ISSN. 2248-9962 www.ijera.com vol.2 issue 3, may-June 2012, pp-2 2305-2311.
[4] Shamanth H. K. , Venkatesh Kumar. H "Digital Implementation Of 6-bit SAR ADC with Foreground Technology" International Research Journal of Engineering & Technology [IRJET] volume 03, Issue 07 / July-2016 e-ISSN 2395-0056 p-ISSN 2395-0072 Nagarjuna College Of Engineering Bangaluru.

ABSTRACT: This paper intends to reduce musical noise, a bi-product of subtractive type methods of speech enhancement technique which degrades the quality of the speech signal. Hamming Window is most commonly used in Speech Enhancement systems to estimate power spectrum, but it has high variance which in turn degrades the speech quality. To reduce this high variance, Multitaper window is used in the proposed model as a spectral estimator. Reduction in the variance of spectral estimate of noise improves the performance of spectral subtraction algorithms..........

Keywords: Multi-band Spectral Subtraction, Multitaper Spectral Estimation, Musical Noise, Speech Enhancement, Variance

1] Thomson, D.J., "Spectrum estimation and harmonic analysis," Proceedings of the IEEE, 70, 1055-1096, 1982.
[2] S.F. Boll, "Suppression of acoustic noise in speech using spectral subtraction," IEEE Trans. Acoust., Speech.
[3] H. Gustafsson, S. Nordholm, I. Claesson, "Spectral subtraction using reduced delay convolution and adaptive averaging," IEEE Trans. Speech Audio Process. 9(2001) 799–807.
[4] S. Kamath, and P. C. Loizou, "A multi-band spectral subtraction method for enhancing speech corrupted by colored noise," in Proceedings of Int. Conf. on Acoustics, Speech, and Signal Processing, Orlando, USA, May 2002, vol. 4, pp. 4160 4164.
[5] D. B. Percival and A. T. Walden, "Spectral Analysis for Physical Applications: Multitaper and Conventional Univariate Techniques," Cambridge, MA: Cambridge Univ. Press, 1993.

ABSTRACT: The binary addition is the basic arithmetic operation in digital circuits and it became essential in most of the digital systems including ALU, microprocessors and DSP. Adders are the basic building blocks in digital integrated circuit based designs. Ripple Carry Adder (RCA) gives the most compact design but takes longer computation time. The time critical applications use Carry Look-ahead scheme (CLA) to derive fast results but they lead to increase in area...........

Keywords: Carry select adder, Verilog, Power, delay, Modelsim6.5b, Xilinx ISE14.7. Co

[1]. B. Ramkumarnd Harish M Kittur, "Low Power and Area Efficient Carry Select Adder" IEEE Transactions on Very Large Scale Integration (VLSI) Systems, VOL. 20, NO. 2, February 2012. [2]. B. Ramkumar, Kittur, H.M. and Kannan, P. M. (2010) "ASIC Implementation of Modified Faster Carry Save Adder", Eur. J. Sci. Res., Vol.42, No.1, pp.53–58. [3]. C.S.Manikandababu "An Efficient CSLA Architecture for VLSI Hardware Implementation" IJMIE, ISSN: 2249-0558, Volume 2, Issue 5, 2012, pp.610-622. [4]. Arunprasath S et al., "VLSI Implementation and Analysis of Parallel Adders for Low Power Applications", International Journal of Computer Science and Mobile Computing, Vol.3 Issue.2, February- 2014, pg. 181-186.
[5]. Shivani Parmar and Kirat Pal Singh," Design of High Speed Hybrid Carry Select Adder", IEEE's 3rdinternational advance Computing Conference Ghaziabad, ISBN: 978-1-4673-4527-9, 22-23 February2013

ABSTRACT: The proposed work is to design and implement VGA (Vedio Graphics Array )Controller on FPGA, as a standard display interface, it is widely used. The controller is developed using Verilog HDL (Hardware description language) . It is implemented on FPGAs chip of Altera DE2-115 Development and Educational Board. The system will display the image on the monitor screen and test the design on the FPGA board

Keywords: VGA Controller; Altera Quartus II; DE2-115 Development Board,Verilog HDL

[1] Fangqin Ying, XiaoqingFeng, "Design and Implementation of VGA Controller Fangqin Ying, XiaoqingFeng, "Design and Implementation of VGA Controller Using FPGA", International Journal of Advancements in Computing Technology (IJACT), Vol. 4, No. 17, pp. 458-465, Sep 2012.
[2] Ila.Nagarjuna, Pillem. Ramesh, "An FSM Based VGA Controller with 640×480 Resolution", International Journal of Engineering and AdvancedTechnology (IJEAT), Vol. 2, Issue – 4, pp. 881-885, April 2013.
[3] M.Bharathi and A.Yogananth, "Design of VGA monitor control using Altera FPGA based system" International Journal of VLSI and Embedded Systems (IJVES), Vol. 5, pp. 866-870, March 2014
[4] Wayne Wolf, "FPGA-Based System Design", Pearson Education Inc., India, 2004.
[5] SamirPalnitkar, Verilog HDL: A Guide to Digital Design and Synthesis", Sun Microsystems, Inc., USA,2003

ABSTRACT: The polar encoding is one among the most effective error correcting code attributable to the channel achieving property. It finds its application in communication, information theory. This coding technique proposed by Eardal Arikan is significant because of its zero errors and simple architecture designed for hardware implementation. Although the fully parallel encoder is intuitive and easy to implement, but it is not suitable for long polar codes because of its hardware complexity. In this brief, we analyze the encoding process in the viewpoint of very-large-scale integration and implement a efficient encoder architecture that is suitable for long polar codes and effective in the hardware complexity. It can be applicable to the design of any polar code and at any level of parallelism.

Keywords: Partially parallel encoder, long polar codes, VLSI implementation

[1]. E. Arikan, "Channel polarization: A method for constructing capacity achieving codes for symmetric binary-input memoryless channels," IEEETrans. Inf. Theory, vol. 55, no. 7, pp. 3051–3073, Jul. 2009.
[2]. R.Mori and T. Tanaka, "Performance of polar codes with the construction using density evolution," IEEE Commun. Lett., vol. 13, no. 7, pp. 519– , Jul. 2009.
[3]. S. B. Korada, E. Sasoglu, and R. Urbanke, "Polar codes: Characterization of exponent, bounds, constructions," IEEE Trans. Inf. Theory, vol. 56, no. 12, pp. 6253–6264, Dec. 2010.
[4]. I. Tal and A. Vardy, "List decoding of polar codes," in Proc. IEEE ISIT, 2011, pp. 1–5.
[5]. K. Chen, K. Niu, and J. Lin, "Improved successive cancellation decoding of polar codes," IEEE Trans. Commun., vol. 61, no. 8, pp. 3100–3107, Aug. 2013
[5] SamirPalnitkar, Verilog HDL: A Guide to Digital Design and Synthesis", Sun Microsystems, Inc., USA,2003