iosr-JVSP   Volume-6 ~ Issue-6 ~ Nov-Dec 2016

ABSTRACT: The Karplus-Strong (KS) algorithm is the popular audio synthesis algorithm which synthesizes the sound of a plucked string at low computational complexity. Though it was classified as a wavetable synthesis technique, later it was shown to be a special case of more general physical modeling technique. A plucked string sound is rich in harmonics, slowly looses the higher harmonics and eventually reaches a steady state single tone signal. In this paper a systematic study is carried out to investigate the effect of wavetable on the time evolution of the spectrum of KS generated guitar notes. The results of this study are useful for the synthesis and classification of virtual instruments that use plucked strings, and also in melody extraction from instrumental music.

Keywords: Guitar notes; plucked string; audio synthesis; fret board; STFT analysis, spectral peak tracking

[1]. R.A. Waldron Waves & Oscillations D. Van Nostrand Co. Inc. 1964
[2]. Neville H. Fletcher, Thomas Rossing, "The Physics of Musical Instruments", Second Edition, Springer, 1998
[3]. Kelvin Karplus and Alex Strong, "Digital Synthesis of Plucked-String and Drum Timbres," Computer Music Journal, vol. 7, No. 2,
pp. 43-55, Summer 1983.
[4]. D. A. Jaffe, and J. O. Smith, "Extensions of the Karplus-Strong Plucked-String Algorithm," Computer Music Journal, vol. 7, No. 2,
1983, pp. 56-69.
[5]. Smith, Julius O. , Physical Audio Signal Processing, W3K Publishing, http://books.w3k.org/, ISBN 978-0-9745607-2-4.

ABSTRACT: The automotive industry is working to develop the Dedicated Short-Range Communication (DSRC) technology. It is an emerging technique and key enabling technology to push the intelligent transportation system with safety applications into our daily life. The DSRC standards generally make use of FM0 and Manchester codes to have good dc-balance, enhancing the signal reliability. The distinguishable coding-diversity between the FM0 and Manchester codes causes a serious limitation to design fully reused VLSI architecture for both the codes...........

Keywords: Dedicated Short Range Communication (DSRC), FM0, Manchester, SOLS, VLSI.

[1]. Yu-Hsuan Lee, Cheng-Wei Pan, "Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique for DSRC Applications," IEEE VLSI systems, vol. 23, no. 1, pp. 18-29, Jan. 2015.
[2]. F. Ahmed-Zaid, F. Bai, S. Bai, C. Basnayake, B. Bellur, S. Brovold et al., "Vehicle safety communications—Applications (VSC-A) final report," U.S. Dept. Trans., Nat. Highway Traffic Safety Admin., Washington, DC, USA, Rep. DOT HS 810 591, Sep. 2011.
[3]. J. B. Kenney, "Dedicated short-range communications (DSRC) standards in the United States," Proc. IEEE, vol. 99, no. 7, pp. 1162–1182, Jul. 2011.
[4]. J. Daniel, V. Taliwal, A. Meier, W. Holfelder, and R. Herrtwich, "Design of 5.9 GHz DSRC-based vehicular safety communication," IEEE Wireless Commun. Mag., vol. 13, no. 5, pp. 36–43, Oct. 2006.
[5]. P. Benabes, A. Gauthier, and J. Oksman, "A Manchester code generator running at 1 GHz," in Proc. IEEE, Int. Conf. Electron., Circuits Syst., vol. 3. Dec. 2003, pp. 1156–1159..

ABSTRACT: The main aim of this project is to design a low-power Content-Addressable Memory (CAM) by applying an algorithm for associativity between the input tag and the address of the corresponding output data. This architecture is based on a recently developed sparse clustered networks using binary connections that on-average eliminates most of the parallel comparisons which are performed during a search. Therefore, the dynamic energy consumption of this design will be less compared to conventional low-power CAM design. Given an input tag, this architecture will compute a minimum number of possibilities for the location of the matched tag and it will perform the comparisons on them to locate a single valid match.

Keywords: CAM, SCN-CAM, Tag

[1]. K. Pagiamtzis and A. Sheikholeslami, "Content-addressable memory (CAM) circuits and architectures: A tutorial and survey," IEEE J. Solid-State Circuits, vol. 41, no. 3, pp. 712–727, Mar. 2006.
[2]. H.Jarollahi, Vincent Gripon, Naoya Onizawa, "Algorithm and Architecture for a Low-Power Content Addressable Memory based on Sparse Clustered Networks", in IEEE Trans., on VLSI, vol 23, No. 4,April 2015.
[3]. Kyle Locke "Parameterizable Content Addressable Memory" in XAPP1151, vol1.0, March. 2011

[4]. P.-T. Huang and W. Hwang, "A 65 nm 0.165 fJ/Bit/Search 256 × 144 TCAM macro design for IPv6 lookup tables," IEEE J. Solid-StateCircuits, vol. 46, no. 2, pp. 507–519, Feb. 2011
[5]. H. Noda et al., "A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture," IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 245–253, Jan. 2005..

ABSTRACT: In this paper the effects of choosing a proper Utilization Factor on total wire length, time to place & route and DRC violations have been explained clearly. In addition, how the number of metals layer used to route between the standard cells will affect total wire length, and number of DRC (Design Rule Constraints) violations and time to place and route at different utilization factors has been studied. It's observed that If the design has high utilization factor then power planning should be done on higher metal layers to avoid DRC violations and less time to place and route

Keywords: Floor Plan, PG planning, Place and Route, Utilization Factor. Time to Place & Route.

[1]. Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic, Digital Integrated Circuits, 2nd Edition (Prentice Hall, ISBN 978-81- 203-2257-8).
[2]. Choosing Appropriate Utilization Factor and Metal Layer Numbers for an Efficient Floor Plan in VLSI Physical Design.
[3]. R. Ho, K. W. Mai, and M. A. Horowitz, , "The future of wires" , Proc. IEEE , vol. 89 , no. 4 , pp.490 -504 , 2001
[4]. P. Cocchini, , "Concurrent flip-flop and repeater insertion for high performance IC" , Proc. IEEE Int. Conf. Computer- Aided Design , pp.268 -273 , 2002
[5]. W. Liao and L. He, , " Interconnect of Full chip Power Estimation and simulation considering concurrent repeater and flip-flop insertion" , Proc. IEEE Int. Conf. CAD , pp.574 - 580 , 2003.

ABSTRACT: The Finite Impulse Response (FIR) filters are widely used in many Digital Signal Processing (DSP) applications. For these applications, the low power, less area, high speed and low complexity FIR filter architectures are required. The researchers have proposed many FIR filters to meet the above design specifications. This paper is focused on the some efficient reconfigurable FIR filter architectures. The author Mohanthy et. al introduced a FIR filter architecture implemented for higher order fixed and reconfigurable applications. This filter is a block FIR filter, which realized in transpose-form configuration with less area, low power and less delay for large order filters. The second filter architecture in this paper is a custom reconfigurable power efficient FIR filter using multiplier less (Reduced Adder Graph) RAG-N Algorithm. In this method, the multiplier is realized using adders and shifters. This architecture is easy to implement, symmetrical and stable system...............

Keywords: FIR, Low power, Booth encoder, Wallace tree multiplier, VLSI, MCM and RAG-N.

[1]. V. Sandhiya, S. Karthick & M.Valarmathy, "A survey of new reconfigurable Architectures for implementing fir filters With low complexity" IEEE Int. Conf. on Computer Communication and Informatics (ICCCI -2014), Jan, 2014.
[2]. B. K. Mohanty & P. K. Meher "A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications" IEEE Trans. VLSI Syst.,Vol. 24 issue.2 ,pp. 444-452, 2016.
[3]. R. Sakthivel, I. Mishra, Vrushali Jalke & Asmitha Wachaspati " A custom Reconfigurable Power efficient FIR Filter" IEEE Int. Conf. on circuit , power and Computing Technologies, pp. 1-4, 2016.
[4]. L. B. Soares, E. A. Ce´sar da Costa & S. Bampi "Design of area and energy-efficient digital CMOS FIR filters with approximate adder circuits" Analog Integr Circ Sig Process, Springer journal, 2016.
[5]. E. Kyritsis & K. Pekmestzi "Hardware Efficient Fast FIR Filter Based on Karatsuba Algorithm" IEEE Int. Conf. on Modern Circuits and systems technologies (MOCAST), pp. 1-4, 2016.

ABSTRACT: This paper is based on design and analysis of proposed 5T SRAM which consumes low power and occupies less area compared to conventional designs. Proposed design consumes low power as dedicated bit line is charged for write and dedicated bit line for read operation. To ensure stability of the cell and reduce flipping of the content during read operation, dedicated circuit is used with separate discharge path for read bit line. This design is developed using 28nm FDSOI-UTBB architecture to keep low power consumption. Proposed design has been analyzed for read/write delay and Write Noise Margin (WNM). The simulated results for read 0, write 1, write 0 are 0.30 ns, 0.17 ns and 0.41 ns, respectively. This design is highly stable for read operation due to its robust architecture and further analyzed for WNM at different sizes. The minimum WNM is found to be 379.77 mV at width of pull-up =200 nm and pull-down=200nm.

[1] S. Borkar, T. Karnik, S. Narendra, J.T schanz, A. Keshavarzi, and V.de,"Parameter Variations and Impact on Circuits & Microarchitecture,"
[2] Proceedings of Design Automation Conerence., pp. 338-342, Jun.2003
[3] Jawar Singh, DhirajK.Pradhan et al,"A single ended 6T SRAM cell design for ultra low voltage applications", IEICE Electronic Express,2008,pp-750-755
[4] Budhaditya Majumdar, Sumana Basu, "Low Power Single Bitline 6T SRAM Cell With High Read Stability", International Conference on Recent Trends in Information Systems, 2011
[5] Lu Wei-YuanUC San Diego Electronic Theses and Dissertations https://escholarship.org/uc/item/4tc4q3zk

ABSTRACT: In today's modern life high speed devices are the essential components of daily human life to reduce efforts of day to day works. For this reason those device must be able to operate at very high speed. To increase the operating speed, normally multi-core processing architecture is used. In those cases, the total task is sub-divided into multiple tasks and each processing cores are executing a particular task in parallel manner. But to calculate accurate value of the total task the individual processors must share some of the variables depending upon the task. So, bi-directional communication is necessary between all processing elements present in the multi-core system. But many issues occur in normal bus architecture to support this kind of communications. This case Network-On-Chip (NoC) router is suitable. In this paper we propose four port NoC router which can operate at high speed by consuming less area.

Keywords: FPGA Architecture, Matrix Switch, Network Architectures, NoC and VLSI Techniques etc.

[1]. B. Forouzan, "Data Communication and Networking", Tata McGraw Hill, 4th Edition, 2006.
[2]. Minu Mathewand and D Mugilan, "Reconfigurable Router Design for Network-On-Chip", International Conference on Circuit, Power and Computing Technologies, pp. 1268-1272, India, March 2014.
[3]. Nasim Nasirian and Magdy Bayoumi, "Low-Latency Power-Efficient Adaptive Router Design for Network-on-Chip", 28th IEEE International System-on-Chip Conference, pp. 287-291, China, September 2015.
[4]. Shaoteng Liu, Axel Jantsch and Zhonghai Lu, "Analysis and Evaluation of Circuit Switched NoC and Packet Switched NoC", 16th Euromicro Conference on Digital System Design, pp. 21-28, California, September 2013.
[5]. Somashekhar Malipatil and Rekha S, "Design and Analysis of 10 PortRouters for Network on Chip (NoC)", International Conference on Pervasive Computing, pp. 1-3, India, January 2015.

ABSTRACT: This paper describes a low-power (LP) programmable generator producing pseudorandom test patterns with desired toggling levels and enhanced fault coverage gradient compared with the best-to-date built-in-self-test(BIST)-based pseudorandom test pattern generators. It is comprised of a linear finite state machine driving an appropriate phase shifter, and it comes with a number of features allowing this device to produce binary sequences with preselected toggling (PRESTO) activity. We introduce a method to automatically select several controls of the generator offering easy and precise tuning. State of the development in the semiconductor manufacturing process.........

Keywords: PRESTO, Switching activity, LFSR,BIST, Scain Design, LP Decompressor

[1] MichałFilipek―Low-Power Programmable PRPG With Test Compression Capabilities"IEEE Transactions on very large scale
integration (vlsi) systems, vol. 23, no. 6, June 2015 .patterns,‖ in Proc. Int. Test Conf. (ITC),2000,pp. 115–122.
[2] A. S. Abu-Issa and S. F. Quigley, ―Bit-swapping LFSR for low-powerBIST,‖ Electron.Lett., vol. 44, no. 6, pp. 401–402, Mar. 2008.
[3] S. Bhunia, H. Mahmoodi, D. Ghosh, S. Mukhopadhyay, and K. Roy,―Low-power scan design using first-level supply gating,‖
IEEE Trans.Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 3, pp. 384–395,Mar.2005.
[4] M. Chatterjee and D. K. Pradham, ―A novel pattern generator for nearperfect fault-coverage,‖ in Proc. 13th IEEE Very Large Scale
Integr.(VTSI) Test Symp., Apr./May 1995, pp. 417–425.
[5] F. Corno, M. Rebaudengo, M. S. Reorda, G. Squillero, and M. Violante,―Low power BIST via non-linear hybrid cellular automata,‖ in Proc.18th IEEE Very Large Scale Integr. (VTSI) Test Symp.,May2000,pp.29–34.
D. Das and N. A. Touba, ―Reducing test data volume using external/LBIST hybrid test patterns,‖ in Proc. Int. Test Conf. (ITC),
2000,pp.115–122.