iosr-JVSP   Volume-7 ~ Issue-4 ~ Jul-Aug 2017

ABSTRACT: Digital image processing is a widely used field in technology. In most of the cases the processing of image is done through computer simulation techniques. This will make the implementation easier. But as the complexity of the algorithm/architecture increases the simulation time also increase accordingly which makes the architecture is unsuitable for real time high speed applications. To overcome from this problem mainly hardware architecture is used. In this paper we propose an FPGA implementation of edge detection architecture using modified Canny edge algorithm and adaptive threshold technique. To obtain optimization in both hardware and output accuracy we change the total architecture in suitable way. The comparison results shows that the proposed design is better than existing.

 

Keywords: Adaptive threshold Calculation, Edge Detection, FPGA Implementation, Image Processing etc..

[1]. [Online] https://en.wikipedia.org/wiki/Canny_edge_detector
[2]. Rafael C Gonzalez and Richard E Woods, "Digital Image Processing", 3rd Edition, Prentice Hall, 2008.
[3]. Mohamed Nasir Bin Mohamed Shukor, Lo Hai Hiung, Patrick Sebastian, "Implementation of Real-time Simple Edge Detection
on FPGA", International Conference on Intelligent and Advanced Systems, 2007.
[4]. Zhengyang Guo，Wenbo Xu and Zhilei Chai, "Image Edge Detection Based on FPGA", Ninth International Symposium on
Distributed Computing and Applications to Business Engineering and Science, 2010.
[5]. Ferdous Hossain, Mithun Kumar P.K. and Mohammad Abu Yousuf, "Hardware Design and Implementation of Adaptive Canny
Edge Detection Algorithm", International Journal of Computer Applications, Vol. 128, No. 9, pp. 31-38, 2015

ABSTRACT: Hardware acceleration in digital signal processing (DSP) domain proved as the best implementation strategy. Overall performance of DSP processor accelerates by using the hardware module named as DSP accelerator by performing certain functions in the accelerator. In some areas such as video processing, flexible DSP accelerator is used to do video encoding and decoding flexibly. The architecture of data path impacts the efficiency of the accelerator. So there is a need to implement flexible data path architecture using Flexible Computational Unit (FCU). This paper solves the problem of developing high-speed and area efficient data path architecture for flexible accelerator, where there is............

 

Keywords: Flexible Data Path, Flexible Computational unit (FCU), Digital Signal Processor, Carry Save Arithmetic.

[1]. J.G. Proakis and D.G. Manolakis, Digital Signal Processing: Principles, Algorithms and Applications. Upper Saddle River, NJ,
Upper Saddle River, NJ, USA:Prentice-Hall, 1996.
[2]. Andrea Lodi, Mario Toma, Fabio Campi, Andrea Cappelli, Roberto Canegallo, and Roberto Guerrieri, "A VLIW Processor with
Reconfigurable Instruction Set for Embedded Applications," Ieee Journal of Solid- state Circuits, Vol. 38, No. 11, November
2003.
[3]. M.D. Galanis, G. Theodoridis, S. Tragoudas, and C.E. Goutis, "A high performance data path for synthesizing DSP Kernels, "
IEEE Trans. Comput- Aided Design Integr. Circuit Syst, vol. 25, no.6, pp.1154-1162, June 2006.
[4]. S. Xydis, G. Economakos, and K. Pekmestzi, "Designing Coarse-grain reconfigurable architectures by inlining flexibility into
custom arithmetic data paths," Integr, VLSI J, vol. 42, no. 4, pp. 486-503, Sep. 2009.
[5]. S. Xydis, G. Economakos, D. Soudris, and K. Pekmestzi, "High Performance and area efficient flexible DSP data path
synthesis," IEEE Trans. Very Large Scale Integr.(VLSI) Syst., vol. 19, no. 3, pp.429-442, Mar.2011..

ABSTRACT: Moore's law will eventually reach its limits as complementary metal-oxide semiconductors (CMOS) are reaching their maturity around the year 2020.There is a need for new chip manufacturing techniques to enable the continuation of law The electronics design needs to shift towards devices that are not only minutely small but increasingly capable and scalable. Memristor devices are an important component in fulfilling these needs. In order to be used effectively in the analysis, design and simulation of memristor based circuits it is important that it should be modeled properly. Previous memristor models incorporated a tunnel barrier model but they employed a time rate change in tunnel width which was strictly based on empirical fitting with memristor data. This paper covers our work in developing heuristic model and discussing its performance.

 

Keywords: Memristor, heuristic model.

[1] P. K. Bondyapadhyay, "Moore's Law Governs the Silicon Revolution," Proceedings of the IEEE, vol.86, no.1, pp.78-81, January 1998.
[2] G. E. Moore, "Cramming more Components onto Integrated Circuits," Electronics, vol.38, no.8, April 1965.
[3] B. G. Streetman and S. K. Banerjee, "Integrated Circuits," Solid State Electronic Devices, 6th ed. New Jersey, USA: Princeton Hall, 2006, ch.9, sec.2, pp.441.
[4] http://www.extremetech.com/computing165331-intels-former-chief-architect-moores-law-will-be-dead-within-a-decade, accessed on March 28, 2014.
[5] R. K. Cavin, P. Lugli and V. V. Zhirnov, "Science and Engineering Beyond Moore's Law," Proceedings of IEEE, vol.100, pp.1720-1749, May 2012.

ABSTRACT: A unique pipelined architecture implementation of adaptive filter based on Distributed Arithmetic (DA) for low-power, high-throughput and low-space. Filtering process involves more space and is not used for higher order filters, therefore it provides a great attrition in the throughput. These are problems that have been overcome by effectual DA formulation of adaptive filters. Distributed Arithmetic is an efficacious procedure for calculating the inner products between a fixed and a variable data vector. Equivalent appliance of 4-point inner product and coefficients increments units to produce immense throughput rate. Carry-save accumulation is used in order to rebate the sampling period and expanse...........

 

Keywords: Adaptive FIR filter, Carry save accumulation, DA, Least Mean Square theorem.

[1] S.Y.Park & P.K.Meher," Low-power, High-throughput and Low-area adaptive Fir filter based on DA", IEEE Trans. on Ckts. and Syst. 2015.
[2] S.Haykin, "Least Mean Square Adaptive filters", Hoboken, NJ, USA: Wiley, 2003.
[3] A.Peled and B.Liu, "A new hardware realization of digital filters", IEEE Transactions on Acoustics, Speech and signal processing, vol.22, pp.456-462, December 1974.
[4] S.A.White ,"Applications of the distributed arithmetic to digital signal processing: A tutorial review," IEEE ASSP Mag., vol6,no.3,pp.4-19,July 1989.
[5] Q.Zhu, S.C.Douglas and K.F.Smith, "A pipelined architecture for LMS Adaptive FIR filters without adaption delay", 0-8186-7919-0/97 1997 IEEE.

ABSTRACT: If the delay of the manufactured network exceeds the specifications due to some physical defects or process variations, non-confidential logic values may be latched in memory elements. The method proposed here combines the static timing analysis techniques and the dynamic timing analysis techniques in combinational circuit timing verification. The framework proposed here combines the static timing analysis(STA) techniques and the dynamic timing analysis(DTA) techniques in the presence of transition delay fault model. Our framework takes the timing violations paths.............

 

Keywords: High-Risk paths, Delay fault model, false paths, Pessimism

[1]. Tsung-Wei Huang,et.al, "UI-Timer: An Ultra-Fast Clock Network Pessimism", IEEE, 2014
[2]. Tsung-Wei Huang, "OpenTimer: A High-Performance Timing Analysis Tool", IEEE, 2015
[3]. CHIN JEN LIN and SUDHAKAR M. REDDY, "On Delay Fault Testing in Logic Circuits", 1987 IEEE
[4]. michael l. bushnell, essentials of electronic testing for digital, memory and mixed-signal vlsi circuits(Kluwer Academic Publishers, 2002)417-439

[5]. T. 1. Kirkpatrick N. R. Clark, "PERT as an Aid to Logic Design", IBM JOURNAL * MARCH 1966.

ABSTRACT: Network on chip technology will be a major factor in future communication system which is based on intra core system, But when comes to power usage this practical NoC system consumes considerably huge power , then the Architecture of the crossbar routers will directly increases with respect to the no of intra core system . When comes to bulky systems, the average power consumption in crossbar switches relatively high. While detailing the components of the routers we found that buffers in the input terminals leads to major power consumption, when we try to remove buffers in NoC routers, the overall performance will reduce due to the bottleneck Increase. To make These Network on Chip.............

 

Keywords: Low Power, Network on Chip, Bufferless, Bottleneck Algori.

[1]. Ahmed Aldammas.: The efficiency of buffer and buffer-less data-flow control schemes for congestion avoidance in Networks on Chip. In: Journal of King Saud University – Computer and Information Sciences, pp. 96–112 (2016)
[2]. Carloni, L.P., Pande, P., Xie, Y.: Networks-on-chip in emerging interconnect paradigms: advantages and challenges. In: Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, pp. 93–102 (2009)
[3]. Rahmani, A.-M., Latif, K., Vaddina, K.R., Liljeberg, P., Plosila, J., Tenhunen, H.: Congestion aware, fault tolerant and thermally efficient inter-layer communication scheme for hybrid NoC-bus 3D architectures. In: Proceedings of the 5th ACM/IEEE International Symposium on Networks-on-Chip, pp. 65–2 (2011).
[4]. Feero, B.S., Pande, P.P.: Networks-on-chip in a three-dimensional environment: a performance evaluation. IEEE Trans. Comput. 58(1), 32–45 (2009
[5]. Pavlidis, V.F., Friedman, E.G.: 3-D topologies for networks-on-chip. IEEE Trans. Very Large Scale Integr. Syst. 15(10), 1081–1090 (2007).

ABSTRACT: Adders are main component used in Digital signal processing (DSP) and are usually used in the digital integrated circuits. In Very-large-scale integration (VLSI) application delay, power and area are the necessary factors for any digital circuits. This paper presents 8 bit parallel adder mapped in Cadence Encounter(R) RTL Compiler Version v14.20-s013_1. By efficiently mapping in cadence tool, area, power and delay are decreased. The results of mapping are viewed using RTL synthesis tool in cadence VIRTUOSO at 45nm technology 0.7V. Based on digital signal processing (DSP) architectures, the code for low power is generated using 8 bit Carry Look ahead adder.

 

Keywords: High-Level Synthesis, Power Optimization, low Area, High Speed, low voltage, parallel adder, DSP, VLSI

[1] Hoang Anh Du Nguyen, Lei Xie,Mottaqiallah Taouil, Razvan Nane,Said Hamdioui, and Koen Bertels,"On the Implementation of Computation-in-Memory Parallel Adder",IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) YSTEMS,1063-8210 © 2017 IEEE, www.ieee.org.
[2] Alex F. Kirichenko, Igor V. Vernik,John A. Vivalda, Rick T. Hunt, and Daniel T. Yohannes,"ERSFQ 8-Bit Parallel Adders as a Process Benchmark",IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, VOL. 25, NO. 3, JUNE 2015,http://www.ieee.org.
[3] H. Esmaeilzadeh, E. Blem, R. S. Amant, K. Sankaralingam, and D. Burger, "Dark silicon and the end of multicore scaling," in Proc. 38th Annu. Int. Symp. Comput. Archit. (ISCA), Jun. 2011, pp. 365–376.
[4] S. Kaxiras, Architecture at the End of Moore (Advances in Atom and Single Molecule Machines). Berlin, Germany: Springer-Verlag, 2013.
[5] Y. Taur, "CMOS design near the limit of scaling," IBM J. Res. Develop., vol. 46, nos. 2–3, pp. 213–222, Mar. 2002.