iosr-JVSP   Volume-4 ~ Issue-1 ~ Jan-Feb 2014

ABSTRACT: In speech analysis, the voiced-unvoiced decision is usually performed in extracting the information from the speech signals. In this paper, we performed two methods to separate the voiced- unvoiced parts of speech from a speech signal. These are zero crossing rate (ZCR) and energy. In here, we evaluated the results by dividing the speech sample into some segments and used the zero crossing rate and energy calculations to separate the voiced and unvoiced parts of speech. The results suggest that zero crossing rates are low for voiced part and high for unvoiced part where as the energy is high for voiced part and low for unvoiced part. Therefore, these methods are proved more effective in separation of voiced and unvoiced speech.

Key woeds: Devnagari script, zero crossing rate,energy of speech signal.

[1] Bachu R.G., Kopparthi S., Adapa B., Barkana B.D.Separation of Voiced and Unvoiced using Zero crossing rate and Energy of the Speech Signal
[2] Jong Kwan Lee, Chang D. Yoo, "Wavelet speech enhancement based on voiced/unvoiced decision",Korea Advanced Institute of Science and Technology The 32nd International Congress and Exposition on Noise Control Engineering, Jeju International Convention Center, Seogwipo, Korea,August 25-28, 2003.
[3] B. Atal, and L. Rabiner, "A Pattern Recognition Approach to Voiced-Unvoiced-Silence Classification with Applications to Speech Recognition," IEEE Trans. On ASSP, vol. ASSP-24, pp. 201-212, 1976. [3] S. Ahmadi, and A.S. Spanias, "Cepstrum-Based Pitch Detection using a New Statistical V/UV Classification Algorithm," IEEE Trans. Speech Audio Processing, vol. 7 No. 3, pp. 333-338, 1999.
[4] Y. Qi, and B.R. Hunt, "Voiced-Unvoiced-Silence Classifications of Speech using Hybrid Features and a Network Classifier," IEEE Trans. Speech Audio Processing, vol. 1 No. 2, pp. 250-255, 1993.
[5] L. Siegel, "A Procedure for using Pattern Classification Techniques to obtain a Voiced/Unvoiced Classifier", IEEE Trans. on ASSP, vol. ASSP-27, pp. 83- 88, 1979.
[6] T.L. Burrows, "Speech Processing with Linear and Neural Network Models", Ph.D. thesis, Cambridge University Engineering Department, U.K., 1996.
[7] D.G. Childers, M. Hahn, and J.N. Larar, "Silent and Voiced/Unvoiced/Mixed Excitation (Four-Way) Classification of Speech," IEEE Trans. on ASSP, vol. 37 No. 11, pp. 1771-1774, 1989.
[8] Jashmin K. Shah, Ananth N. Iyer, Brett Y. Smolenski, and Robert E. Yantorno "Robust voiced/unvoiced classification using novel features and Gaussian Mixture model", Speech Processing Lab., ECE Dept., Temple University, 1947 N 12th St., Philadelphia, PA 19122-6077, USA.
[9] Jaber Marvan, "Voice Activity detection Method and Apparatus for voiced/unvoiced decision and Pitch Estimation in a Noisy speech feature extraction", 08/23/2007, United States Patent 20070198251.
[10] Thomas F. Quatieri, Discrete-Time Speech Signal Processing: Principles and Practice, MIT Lincoln Laboratory, Lexington, Massachusetts, Prentice Hall, ISBN-13:9780132429429.

ABSTRACT: In this paper, our main focus is to reduce computation delay proposed in previous FFA algorithm based FIR digital filter. Parallel FIR filter structure with fast finite-impulse response (FIR) along with symmetric coefficients reduces the hardware cost, under the condition that the number of taps is a multiple of 2 or 3. . The proposed parallel FIR structures exploit the inherent nature of symmetric coefficients reducing half the number of multipliers in sub filter section at the expense of additional adders in preprocessing and post processing blocks. Exchanging multipliers with adders is advantageous because adders weigh less than multipliers in terms of silicon area; in addition, the overhead from the additional adders in preprocessing and post processing blocks stay fixed and do not increase along with the length of the FIR filter, whereas the number of reduced multipliers increases along with the length of the FIR filter. The proposed parallel filters uses normal adders (full adder and ripple carry adder) that take more time to execute the program. Therefore, we replaced Ripple Carry Adder (RSA) with Carry Save Adder (CSA) and finally presented the comparison between the timing delays with RSA and CSA. Overall, the proposed parallel FIR structures can lead to significant hardware savings for symmetric convolutions from the existing FFA parallel FIR filter, especially when the length of the filter is large. All the simulations observed in modelsim6.4b simulator, synthesis by Xilinx ISE tool.

Keywords: CSA (carry save adder), FFA, FIR.

[1] Area-Efficient Parallel FIR Digital Filter Structures for Symmetric Convolutions Based on Fast FIR Algorithm Yu-Chi Tsao and Ken Choi
[2] J. G. Chung and K. K. Parhi, "Frequency-spectrum-based low-area low-power parallel FIR filter design," EURASIP J. Appl. Signal Process., vol. 2002, no. 9, pp. 444–453, 2002.
[3] K. K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation. New York: Wiley, 1999.
[4] Z.-J. Mou and P. Duhamel, "Short-length FIR filters and their use in fast nonrecursive filtering," IEEE Trans. Signal Process., vol. 39, no. 6, pp. 1322–1332, Jun. 1991.
[5] J. I. Acha, "Computational structures for fast implementation of L-path and L-block digital filters," IEEE Trans. Circuit Syst., vol. 36, no. 6, pp. 805–812, Jun. 1989.
[6] C. Cheng and K. K. Parhi, "Hardware efficient fast parallel FIR filter structures based on iterated short convolution," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 8, pp. 1492–1500, Aug. 2004.
[7] C. Cheng and K. K. Parhi, "Furthur complexity reduction of parallel FIR filters," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS 2005), Kobe, Japan, May 2005.
[8] C. Cheng and K. K. Parhi, "Low-cost parallel FIR structures with 2-stage parallelism," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 2, pp. 280–290, Feb. 2007.
[9] I.-S. Lin and S. K. Mitra, "Overlapped block digital filtering," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 43, no. 8, pp. 586–596, Aug. 1996.
[10] "Design Compiler User Guide," ver. B-2008.09, Synopsys Inc., Sep. 2008.

ABSTRACT:2.5 GHz narrow band inductive degenerated (LNA) low noise amplifier implemented in a 0.18 μm RF CMOS process which is used in particularly telecommand system for satellite and also for WSN (Wireless sensor networks. The amplifier provides a forward gain (S21) of ˃ 16 db with a noise figure of S11 ˂ 2db. While drawing of 10 mw from 1.8v Supply by using inductive coupled degenerated LNA. General Terms: LNA, Noise figure, gain, linearity.

Keywords: RF CMOS, VLSI Design, Wireless Communications.

[1] B. Razavi, "CMOS technology characterization for analog and RF design, "IEEE J. Solid-State Circuits, vol.34, pp.268276, Mar,1999.
[2] T.H. Lee, "5-GHz CMOS low noise amplifier", IEEE Journal of Solid State Circuits, Vol.32, May,1997.
[3] D. Shaeffer, T. Lee, "A 1.5V, 1.5 GHz CMOS low noise amplifier", IEEE Journal of Solid State Circuits, Vol.32, May 1997.
[4] N.H. Noh, and T.Z.A, Zulkifli "Comparative Studies of the folded Cascode, Current-reuse and the PCSNIM LNA Topologies for W-CDMA Direct Conversion Receiver" in proceedings of the international conference on Robotics Visio, information and signal processing Rovisp 2007 Penong, Malsia, November, 2007.
[5] Paul, Wester "Recent Trends in CMOS LOW Noise Amplifiers" IEEE ECE 1371, Analog Electronics-II
[6] Maximum Dalls Semi conducter "Trippe/Dual/Single-Mode CDMA, LNA/Mixers application note"
[7] P. Litmanuen, P.IK Aluniern, K. Haloven "A 20HHz Submicron CMOS LNA and down conversion mixer" Texus instruments Inc. R.F. Wireless Design 1998 IEEE.
[8] P.R. Gray, P.J. Harst, S.H. Lewis, and R.G Mayor, "Analysis and design of analog integrated circuits", version 4th Edn.,Newyork, wielly 2001. pp 762-802.
[9] A 2.4 GHz LNA is 0.18/micron CMOS Technology "International Conference on VLSI communicationandInstrumentation ICUCI 2011 Proceedings published by International Journal of Computer Applications (IJCA).
[10] PTM Website (online available (Transistors) http://ptm:asu.edu.

ABSTRACT: With the ever increasing growth in microelectronic devices and applications, there is an equally pressing more demand for ensuring product authenticity, security and reliability of the electronic system. The security requirements for most of the applications are crucial and evolving. In addition more sophisticated attacks are being developed every day. These attacks often have much higher impact and essentially no way to compensate for them with additional software counter measure. Hence we introduce PUF (Physical Unclonable Function) system based on clock networks for security purpose. On chip Physical Unclonable Functions (PUFs) are emerging as a powerful security primitive that can potentially solve several security problems. In this paper we proposed a PUF system based on clock network for resolving security issues in the circuits. The main aim is to create an unclonable circuit with the help of clock network, return path and multiplexer (Mux) block. The clock network has number of sink to split the input data. Return path used to pass the signal from clock network to mux network. Mux network has multiplexer, delay buffer and SR latch. The response of the PUF circuit is unclonable bit. PUF is an external device which can be placed in a circuit to avoid cloning of the circuit. A PUF needs to be robust against reversible as well as irreversible temporal changes in circuits. PUF functions promise cheap, efficient and secure identification and authentication of devices. It is impossible to copy the protected circuit by others in an exact manner and cannot get the same functionality of the device. Thus we can protect the device from cloning.

Keywords: Arbiter, Clock network, Sink, Return path, unclonable bit generation.

[1] D.E. Holcomb, W. Burleson, and K. Fu. Power-up SRAM state as an identifying fingerprint and source of true random numbers. IEEE Trans. Comp., 58(9):1198–1210, September 2009
[2] J.W. Lee, A. Lim, B. Gassend, G.E. Suh, M. van Dijk, and S. Devadas. A technique to build a secret key in integrated circuits for identification and authentication applications. In Symp. VLSI, pages 176–179, 2004
[3] F. Armknecht, R. Maes, A.-R. Sadeghi, F.-X. Standaert, and C. Wachsmann. A formalization of security features of physic functions. In IEEE Symp.Sec'ty & Privacy, pages 397–412, 2011.
[4] J. Guajardo, S.S. Kumar, G. Schrijen, and P. Tuyls. FPGA intrinsic PUFs and their use for IP protection. (In Crypto Hardware & Emb Sys (CHES), 2007) 63–80.
[5] B. Gassend, D. Clarke, M. van Dijk, and S. Devadas. Controlled physical random functions.( In ACSAC, 2002) 149–160.
[6] G. Suh and S. Devadas. Physical unclonable functions for device authentication & secret key generation.( In DAC,2007) 9–14.
[7] Defense Science Board (DSB) study on High Performance Microchip Supply, 2005
[8] Defense Industrial Base Assessment: Counterfeit Electronics study by U.S. Dept. Of Commerce Bureau of Industry & Security Office Of Tech. Evaluation, 2010.
[9] R. Maes and I. Verbauwhede. Physically Unclonable Functions: a Study on the State of the Art and Future Research Directions. Springer, 2010
[10] U. Ruhrmair, S. Devadas, and F. Koushanfar. Security Based on Phys. Unclonability and Disorder. Springer, 2011

ABSTRACT: Phased array radar is very important in modern radar development, and multiple digital beams forming technology is the most significant technology in phased array radar. Beam forming is a signal processing technique used in antenna arrays for directional signal transmission or reception. Digital multiple beam forming on each antenna element about large phased array radar is impossible in processor based digital processing units, because it needs simultaneous processing many A/D channels. In this project we resolve this problem by using a multi array based beam forming technique with multiplexed signal processing unit on FPGA. The conventional technique of completely duplicated hardware and also dynamic reconfiguration does not yield the real time parallel beam processing. The proposed technique employs multiplexed signal processing unit which is time shared for various beam formers. This technique provides simultaneous beams without any compromise on functionality.

[1] A dynamically Reconfigurable Phased Array Radar Processing System,Emmanuel Seguin, Russell Tessier, EricKnapp, and Robert W.Jackson
[2] G. W. Stimson: "Introduction to Airborne Radar, 2nd Ed.," SciTech Publishing, 1998
[3] P. Lacombe, J.-P. Harding, J.-C. Marchais, E. Normant: "Air and Spaceborne Radar Systems: An Introduction," IEE, 2001
[4] M. I. Skolnik: "Introduction to Radar Systems, 3rd Ed.," McGraw-Hill, 2005
[5] R. J. Mailloux: "Phased Array Antenna Handbook," Artech House, 2005
[6] E. Brookner: "Practical Phased Array Antenna Systems," Artech House, 1991
[7] R. C. Hansen: "Phased Array Antennas," John Wiley & Sons, 1998
[8] A. Ludloff: "Praxiswissen Radar und Radarsignalverarbeitung, 2. Auflage," Viewegs Fachbücher der Technik, 1998 .

ABSTRACT:Producing designs based on sub-micron technologies at a competitive cost has always been a challenge for the manufacturers. Different Integrated Circuit (IC) implementation approaches have been adopted to reduce the design time and improve manufacturing costs. One of the methods is to use a 'Cell-Based' IC implementation approach using Standard Cell Libraries However, the cost associated with the design or purchase of Standard Cell Libraries (Non-Recurring Expense (NRE)) has been increasing consistently with the shortening of device technology. In this paper we present the development of submicron CMOS Standard Cell Library that is suitable for 45nm CMOS process The intent was to generate a comprehensive library containing core number of necessary cells, providing detailed layout and transistor-level schematic views of every cell, with characterization under the 45nm process, in order to utilize them as a fully synthesizable library. The library is designed using Cadence.

Index Terms: standard cell library, 45nm process, layout design, characterization

[1] Jan M. Rabaey et al., "Digital integrated circuit – A Design Perspective", Second Edition, Prentice Hall, 2003.
[2] HSPICE® Reference Manual: Commands and Control Options Version B-2008.09, September 2008 (Synopsis)
[3] Ashral bin Bahari Tambek, Ahmad Raif bin Mohd Noor Beg, Mohd Rais Ahmad, "Standard Cell Library development", in Proceedings of the 11th International Conference on Microelectronics, 1999, pp.22-24.
[4] Weitong Chuang, Sachin S. Sapatnekar, Ibrahim N. Haji, "Timing and area optimization for Standard-Cell VLSI circuit design", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 14, March 1995.
[5] CMOS IC LAYOUT Concepts, Methodologies, and Tools by Dan Clein
[6] Ron Wilson, EE Times, May 2000.

ABSTRACT:The advancement of technologies for averting drowsiness at the wheel is a key dilemma in the field of accident p r e v e n t i o n systems. Preventing drowsiness during driving necessitates a scheme for precisely perceiving deterioration in driver's vigilance and a means for alerting and reviving the driver. Drowsy Driver Detection System has been developed, using a non-intrusive machine vision based concepts. This system offers a method for driver eye detection, which could be used for observing a driver's fatigue level while he/she is maneuvering a vehicle. The system uses a small monochrome security camera that points directly towards the driver's face and monitors the driver's eyes in order to detect fatigue. In such a case when fatigue is detected, a warning signal is issued to alert the driver. This paper describes the method that has been proposed for finding the eyes,

[1] S. G. Klauer, T. A. Dingus, V. L. Neale, , and J. D. Sudweeks, "The impact of driver inattention on near-crash/crash risk: An analysis using the 100-car naturalistic driving study data," National Highway Traffic Safety Administration, DC, DOT HS, vol. 810, 2006.
[2] T. Akerstedt, G. Kecklund, and L. H¨orte, "Night driving, season, and the risk of highway accidents." Slee, vol. 24, pp. 401–
406, 2001.
[3] J. Connor, R. Norton, S. Ameratunga, E. Robinson, I. Civil, R. Dunn, J. Bailey, and R. Jackson, "Driver sleepiness and risk of
serious injury to car occupants: Population based control study." British Medical Journal, vol. 324, pp. 1125– 1129, 2002.
[4] J. Horne and L. Reyner, "Vehicle accidents related to sleep: A review." Occupational and Environmental Medicine, vol. 56, pp. 189–294, 1999.

ABSTRACT:In Microprocessor power minimization is a major concern. Many circuit and micro-architectural innovations have been proposed to reduce power in many individual processor units. The strategy is used to dynamically and simultaneously adjust the reorder buffer to reduce power dissipation in the data path without significant impact on the performance. Therefore a challenge is to find a centralized approach which can address power issues for one unit with the least amount of redesign and verification efforts and the least hardware overhead. Therefore it proposes such a centralized approach that attempts to simultaneously reduce power in processor unit with highest dissipation in reorder buffer.

[1]. HoumanHomayoun , "reducing power in all major CAM and SRAM based processor units via centralized ,dynamic resource size management"IEEE transactions on Very large scale integration system,vol.19,no.11,nov 2011.
[2]. A. Karandikar and K. K. Parhi, "Low power SRAM design using hierarchical divided bit-line approach," in Proc. Int. Conf. Comput. Des., 1998, pp. 82–88.

ABSTRACT:In this paper, we propose the new moduli set { − , , + } with an efficient reverse converter. Experiments were performed on our converter and the state of the art using Xilinx ISE 14.3 software to target a Spartan 3 FPGA board. The results from these experiments suggest that on the average, the proposed converter outperforms the state of the art converters for the moduli sets { − , , + } and { − , , + }.

Keywords: Residue Number System, Reverse Converter, Moduli Set, Mixed Radix Conversion, Chinese Remainder Theorem.

1] L. Sousa, S. Antão, R. Chaves, On the Design of RNS Reverse Converters for the Four-Moduli Set { + , − , , + } IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 21, no. 10, pp. 1945 - 1949, Oct. 2013.
[2] K.A. Gbolagade, R. Chaves, L. Sousa, and S.D. Cotofana, An Improved RNS Reverse Converter for the n - , n, n- Moduli Set, IEEE International Symposium on Circuits and Systems (ISCAS2010), pp. 2103-2106, Paris, France, June, 2010.
[3] Y. Wang, X. Song, M. Aboulhamid and H. Shen, Adder Based Residue to Binary Number Converters for { − , , + }, IEEE Transactions on Signal Processing, Vol. 50, pp.1772–1779. 2002.
[4] A. Hariri, K. Navi, R. Rastegar, A new high dynamic range moduli set with efficient reverse converter, International Elsevier Journal of Computers and Mathematics with Applications, doi:10.1016/j.camwa.2007.04.028, 2007.
[5] B. Cao, C. H. Chang, and T. Srikanthan, A residue-to-binary converter for a new five-moduli set, IEEE Transactions on Circuits Systems I, Reg. Papers, vol. 54, no. 5, pp. 1041–1049, May 2007.
[6] P. V. A. Mohan and A. B. Premkumar, RNS-to-binary converters for two four-moduli { + , − , , − } and { + , − , , + }, IEEE Transactions on Circuits Systems I, Reg. Papers, vol. 54, no. 6,pp. 1245–1254, Jun. 2007.
[7] S. Lin, M. Sheu, and C. Wang, Efficient VLSI design of residue to binary converter for the moduli set n, n - , n- , IEICE Trans.INF. and SYST., Vol. E91-D, No.7, pp. 2058-2060, July, 2008