iosr-JVSP   Volume-5 ~ Issue-2 ~ Mar-Apr 2015

ABSTRACT: The processors form the main part in all major electronic components in the digitized world. The memory inside the processor consumes more power. The memory of the processor is a register file architecture. The power dissipation of the register file is mainly caused due to Local and Global Bit line circuits. Domino logics are the main components considered in the design of the local and global bit lines. The domino logic circuit suffers mainly due to increased power dissipation because of leakage current in the evaluation network and also due to current contention because of keeper upsizing. In order to avoid such problems the current comparison domino logic is used. Further the performance of the current comparison based domino logic can be increased by including Clock gating concept. So by this unwanted switching can be avoided at times where clock signal is not needed. This fairly reduces the power dissipation. By designing the Local and Global bitlines with this type of domino logic, the performance of the register files can be increased with reduction in power dissipation. Thus the microprocessors and DSPs would have better efficiency.

Keywords: Domino logic, bit lines, register files, clock gating, current comparison.

[1]. Agarwal. A, Hsu. S et all., "A 32-nm 8.3 GHz 64-entry x 32-bit variation tolerant near threshold register file", Proceedings of symposium on VLSI Circuits (VLSIC) technical digest of technical papers, 2010, pp. 105-106.
[2]. Anis. M, Allam. M. W, Elmsary, "Energy Efficient noise tolerant technique for scaled down CMOS and MTCMOS technologies", IEEE Trans, VLSI Syst., vol. 10, no.2, pp. 71-78, Apr 2002.
[3]. Alvandpur. A, Krishnamoorthy. K et all., "A sub 130-nm conditional keeper technique", IEEE Journal of Solid State Circuits 37 (2002) 633-638.
[4]. Bowman. K, Duval. S. G et all., "Impact of die-to-die and within die parameter fluctuations on maximum clock frequency distribution for gigascale integration", IEEE Journal of Solid State circuits, vol. 37, no.2, pp.183-190, Feb 2002.
[5]. David Jeyasingh. R. G, Bhatt. N and Amrutur. B, "Adaptive Keeper design for dynamic logic circuits using rate Sensing technique", IEEE Transactions on Very Large Scale Integration (VLSI) Syst., vol. 19, no.2, pp.295-304, Feb 2011.
[6]. Guan. X, Fei. Y, "Register File Partitioning and Compiler Support for reducing embedded processor power consumption", IEEE Transactions on Very Large Scale Integration (VLSI) systems 18 (2010), 1248-1252.

ABSTRACT: This paper proposes new parallel fir structures to reduce the hardware complexity of higher order Finite Impulse Response (FIR) filter with symmetric coefficients based on Fast FIR Algorithms (FFAs). The objective is to design an area-efficient Fast Parallel Finite-Impulse Response (FIR) filter structure which constraint that the filter taps must be a multiple of 2 or 3. In this brief discussed for three parallel FIR Filter implementation based on recursively using proposed 2 parallel FIR Structure. It exploits the inherent nature of Symmetric co-efficient reducing the number of Multipliers in further. The parallel FIR filter structure based on proposed FFA techniques has been implemented based on Modified carry save adder (MCSA) for further enhancement. The reduction in hardware complexity is achieved by eliminating the bulky multiplier with an adder namely MCSA. Overall, the proposed parallel FIR structures can lead to significant hardware savings for symmetric coefficients from the existing FFA parallel FIR structures, particularly when the length of the filter is very large.

[1]. Yu-Chi Tsao and Ken Choi, "Area-Efficient Parallel FIR Digital Filter Structures for Symmetric Convolutions Based on Fast FIR Algorithm" IEEE Transactions on Veri Large Scale Integration (VLSI) Systems, vol. 20, no. 2, pp. 366–371, Feb. 2012.
[2]. C. Cheng and K. K. Parhi, "Low-cost parallel FIR structures with 2-stage parallelism," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 2, pp. 280–290, Feb. 2007.
[3]. C. Cheng and K. K. Parhi, "Furthur complexity reduction of parallel FIR filters," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS 2005),Kobe, Japan, May 2005.
[4]. C. Cheng and K. K. Parhi, "Hardware efficient fast parallel FIR filter structures based on iterated short convolution," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 8, pp. 1492–1500, Aug. 2004.
[5]. J. G. Chung and K. K. Parhi, "Frequency-spectrum-based low-area low-power parallel FIR filter design," EURASIP J. Appl. Signal Process., vol. 2002, no. 9, pp. 444–453, 2002.

ABSTRACT: As the complexity of the microprocessor design is increasing the verification method is also becoming more and more complex. Unfortunately, it requires a long time to generate and run test sequences. Under the time to market pressure, it is very time consuming to write all test programs manually. This brings about the necessity of developing a random test program generator. The proposed method is for verifying the pre silicon model of the multithreaded multi cored processor (SPARC T1). The work takes the input from the user and generates a sequence of assembly language instructions (SPARC V9) randomly, initializes all the register values with random numbers to verify the corner cases. The test cases are seed based and run through the RTL model to check the correctness of the design. The test cases generated are also run on the defective model.

Keywords: SPARC, SPARC V9, RTPG, Defective model.

[1]. AharonAharon,Dave Goodman, Moshe Levinger, Yossi Lichtenstein,Yossi Malka, CharlotteMetzger, Moshe Molcho, Gil Shurek,Test Program Generation for Functional Verificationof PowerPC Processors in IBM,
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[5]. S. Mehta ,S. Ahmed, S. Al-Ashari, Dennis Chen, et al.Verification of the UltraSPARCTMMicroprocessor IEEE Computer Society Int'l conf., 1995, pp 452-461.

ABSTRACT: The purpose of a transform is to consider an algorithm or a fixed procedure or a set of rules or anyequation that changes one set of data to another set of data. The Fast Fourier Transform which is an efficient way to calculate the Discrete Fourier Transform produces results by first dividing the equation into even and odd terms. A type of Fast Fourier Transform algorithm is Split-Radix where, it uses both radix-2 and radix-4 for its simplicity and efficiency respectively The purpose of this paper is to give review of work done on split-radix algorithm and its advantages when compared to other radix implementations.

Index Terms: Cooley-Tukey algorithm, DFT, FFT, FPGA, split-radix.

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[2]. Wen-Chang Yeh and Chein-Wei Jen, "High Speed and Low-Power Split-Radix FFT", IEEE TRANSACTIONS ON
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[4]. Steven G. Johnson and Matteo Frigo, "Modified Split-Radix FFT With Fewer Arithematic Operations", IEEE
[5]. TRANSACTIONS ON SIGNAL PROCESSING, VOL. 55, NO. 1, JANUARY 2007.
[6]. Henrik V. Sorensen, Michael T. Heideman, and C. Sidney Burrus, "On Computing the Split-Radix FFT", IEEE
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ABSTRACT: Face recognition is a biometric software application that can identify a specific individual in a digital image by analyzing and comparing pattern. In the proposed approach, Here main focus on the face recognition system. It will one of the new face recognition system based on an efficient design. This paper present proposed methodology of global thresholding technique, SIFT (Scale Invariant Feature Transform),PCA(Principal Component Analysis) and SVM (Support Vector Machine) classifier. SIFT is used for extract the feature from faces. This SIFT feature will possess strong robustness to the accessory, expression, pose, illumination variations. PCA is a standard technique use for dimensionality reduction in which face data can analyze and observation can be described by several inter-correlated dependent variables. The SVM classifiers are then applied to these extracted features to classify the input images. Global thresholding technique will used for detecting the face. So this proposed system will increases the face identification rate. Keywords:-Global thresholding technique Biometric, SIFT, PCA, SVM, Face recognition.

[1]. M. A. Turk and A. P. Pentland, "Face recognition using eigenfaces",Proc. Of CVPR' 91., IEEE Computer Society Conference on Computer Vision and Pattern Recogniton, 1991.
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[3]. D. Lowe, "Distinctive image features from Scale-Invariant Keypoints," International Journal of Computer Vision, vol. 60(2), pp. 91-110, 2004.
[4]. Patrik Kamencay, Martin Breznan, Dominik Jelsovka, and Martina Zachariasova, "Improved Face Recognition Method based on segmentation
Algorithm using SIFT-PCA", 978-1-4673-1118-2/12/$31.00 ©2012 IEEE
[5]. Gautam Narang, Soumya Singh Arjun Narang, " Robust Face Recognition Method Based on SIFT Features Using Levenberg-Marquardt Backpropagation Neural Networks", 978-1-4799-2764-7/13/$31.00 ©2013 IEEE

ABSTRACT: In this paper, we have designed D flip-flop using NAND gates. The gates are ternary NAND gates, which are constructed using Neuron MOS transistors. According to D Flip-Flop operation, output will follow the input which is given in the form of ternary logic as 0, 1, 2. A considerable reduction in the number of transistor count is achieved using this new configuration. The circuit simulation is done using T-spice and waveforms are checked using W-edit. The circuit is design using transistor length L=0.18u. Keywords: D flip-flop, Floating-gate, Neuron MOS, Ternary logic, TNAND.

[1]. Tadashi Shibata, Tadahiro Ohmi, "An Intelligent MOS Transistor Featuring Gate-Level Weighted Sum and Threshold Operations," IEDM Tech. Dig, pp. 919-922, 1991.
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[3]. Esther Rodriguez-Villegas, "Low Power and Low Voltage Circuit Design with the FGMOS Transistor", © 2006 The Institution of Engineering and Technology, London, United Kingdom, IET CIRCUITS, DEVICES AND SYSTEMS SERIES 20.
[4]. Neil H. E. Weste, David Harris, Ayan Banerjee, "CMOS VLSI Design A circuit and system Perspective", 3rd edition, Pearson education.
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ABSTRACT: The role of the compression is to reduce bandwidth requirements for transmission & memory requirements for storage of all forms of data as it would not be practical to put images, audio, video alone on websites without compression. The medical community has many applications in image compression often involving various types of diagnostic imaging. The use of wavelet transform is now well established due to its multi resolution & scaling property. Among the various techniques we have used the lifting scheme as it allows perfect reconstruction by its structure. The aim of this paper is to give a review of VLSI architectures for efficient hardware implementation of wavelet lifting schemes. The inherent in place computation of lifting scheme has many advantages over conventional convolution based DWT. The Discrete Wavelet Transform (DWT) has become a very versatile signal processing tool over the last Decade.

Index Terms: Discrete wavelet transform (DWT), FPGA, lifting scheme.

[1]. Joshni C.George, T.Jayachandran, Dr.C.N.Marimuthu, "2D-DWT Lifting Based Implementation using VLSI architecture," IJARECE Volume 2, Issue 3, March 2013.
[2]. Chengyi Xiong, Jinwen Tian, and Jian Liu, "Efficient Architectures for Two-Dimensional Discrete Wavelet Transform Using Lifting Scheme," IEEE TRANSACTIONS ON IMAGE PROCESSING, VOL. 16, NO. 3, MARCH 2007.
[3]. Gab Cheon Jung, Duk Young Jin, Seong MO Park, "An efficient line based VLSI architecture for 2-D lifting DWT,"The 47th IEEE International Midwest Symposium on Circuits and Systems
[4]. Andreas Savakis ,Richard Carbone ,"Discrete wavelet transform core for image processing applications," Rochester Institute of Technology, RIT Scholar Works,2005.
[5]. Kishore Andra,Chaitali Chakrabarti, Tinku Acharya, "Efiicient Implementation of a set of lifting based wavelet filters," Arizona State University, Tempe, Arizona, 85287, USA, Intel Corporation, Chandler, Arizona, USA
[6]. Cheng-Yi Xiong, Jin-Wen Tian, and Jian Liu, "A Note on "Flipping Structure: An Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Transform," IEEE TRANSACTIONS ON SIGNAL PROCESSING, VOL. 54, NO. 5, MAY 2006.

ABSTRACT:It's very important to improve the quality of medical image as it helps in detection of lesion location, for surgery planning and avoid misdiagnosis for surgery. This paper is based on image segmentation, tumor detection and area calculation. In image segmentation of normal magnetic resonance image (MRI) clustering approach is widely used. In this paper FCM (fuzzy c means clustering) is used for bias estimation to remove noise. SKFC (spatial k fuzzy clustering) is proposed for image segmentation. These two algorithms give approximate boundary. Level set after clustering gives the exact boundary for white matter (WM), grey matter (GM), cerebrospinal fluid (CSF) and tumor. After the segmentation of brain MRI, tumor is detected and its exact location is identified. The area of tumor by calculating the white pixels in binary image is proposed to be one of the tumor stage detection parameter. Keywords: Bias estimation; FCM; SKFC; level set; tumor.

[1]. A.Meena, K.Raja "Spatial Fuzzy C-Means PET Image Segmentation of Neurodegenerative disorder".Indian Journal of Computer Science and Engineering (IJCSE)[ISSN : 0976-5166] pp. 50-55
[2]. S.J. Grace Shoba and A. Brintha Therese "A modified spatial fuzzy c-meansclustering algorithm for detecting glaucoma in retinal fundus images" Journal of Computer Science[ISSN: 1549-3636].pp.1362-1372
[3]. Mrs. P. Vijayalakshmi, Selvamani. K, Ms. M. Geetha, "Segmentation of Brain MRI Using K-means Clustering Algorithm" [ISSN:2231-5381]
[4]. Mrs. Bharati R. Jipkate and Dr. Mrs.V.V. Gohokar "A Comparative Analysis of Fuzzy C-Means Clustering and K Means Clustering Algorithms." International Journal Of Computational Engineering Research[ISSN: 2250–3005]pp. 737-739
[5]. Castro, C. Boveda, Arcay "Comparison of various fuzzy clustering algorithms in the detectionof ROI in lung CT and a modified kernelized-spatial fuzzy c-meansalgorithm'' [978-0-7695-4437-3/11 © 2011 IEEE].

ABSTRACT: The main objective of paper is to design and implement a high speed processing system with high throughput and low complexity. We are using system on chip using AMBA bus. This high speed processing system is application specific. This system will be used for landmine detection during wars as high speed processing is need of application. Firstly input processor will be designed as per the application. Then the concurrent processor will be designed. VHDL coding of the entire system on chip will be done. The simulation will be performed using Xilinx and FPGA. After the processing system is designed it will be compared to the conventional controller system. Thus proving that the system on chip is efficient and fast processing than the controller system.

Keywords: Advanced microcontroller bus architecture(AMBA)high performance bus, field programmable gate array(FPGA),landmine detection techniques, system on chip(SoCs)..

[1]. Guoliang Ma and Hu He, "Design and implementation of an advanced DMA controller on AMBA based SoC",2009 IEEE
[2]. ShashisekharRamagundam, Sunil Das, Scott Morton, Satyendra Biswas," Design and implementation of high performance Master/Slave memory controller with microcontroller bus architecture",2014 IEEE.
[3]. Zhenni Li, Jingjiao Li, Yue Zhao, ChaoqunRong," A SoC design and implementation of dynamic image detection based on the LEON3 open source processor",2013 IEEE.
[4]. C. P. Gooneratne, S. C. Mukhopahyay and G. Sen Gupta," A Review of Sensing Technologies for Landmine Detection", 2nd International Conference on Autonomous Robots and Agents December 13-15, 2004 Palmerston North, New Zealand
[5]. Ashutosh Singh, Anurag Shrivastava, G.S.Tomar," Design and implementation of high performance AHB reconfigurable arbiter for on chip bus architecture",2011 IEEE international conference on communication system and network technology

ABSTRACT: In Speaker identification (SI) systems long-lasting feature extraction unit is required. For the purpose of proper representation of this features, there is a speaker modeling scheme after extraction unit. Several feature sets are used for speaker related application, one of the standard feature set is MFCC (Mel Frequency Cepstral Coefficient) which are generally modeled on human auditory system. On the other hand complementary information present in the higher frequency range known as an IMFCC (Inverted Mel Frequency Cepstral Coefficient) is another feature set which is useful. This paper concentrates on Gaussian Mixture Model (GMM)along with the Universal Background Model (UBM) is being used for the modeling purpose. Instead of triangular filters here Gaussian shaped filters are being used. Here , in this paper the results are being verified by the standard database TIMIT. The accuracy for the individual set of features such as for MFCC is coming to be 96.6% for the 16 mixtures while for the IMFCC is 95.4% for the 16 mixtures respectively for first set of speakers used and on other side the accuracy for MFCC and IMFCC in the other set of speakers is 97.22% and 86.11 respectively..

[1]. Fr ´ed´ eric Bimbot,1 Jean-François Bonastre,2 Corinne Fredouille,2 Guillaume Gravier,1 Ivan Magrin-Chagnolleau and Douglas A. Reynolds6 "A Tutorial on Text-Independent Speaker Verification", EURASIP Journal on Applied Signal Processing 2004:4, 430–451c_ 2004 Hindawi Publishing Corporation.
[2]. R.Shantha Selva Kumari a, S. Selva Nidhyananthan ba*, Anand,"Fused Mel Feature sets based Text-Independent Speaker Identification using Gaussian Mixture Model".G c a,bDepartment of ECE, Mepco Schlenk Engineering College , Sivakasi -626005, INDIA cDepartment of ECE, PSRR College of Engineering for Eomen, Sevalpatti,INDIA. International Conference on Communication Technology and System Design 2011
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[5]. International Journal of Information and Communication Engineering, Improved Text-Independent Speaker Identification using Fused MFCC & IMFCC Feature Sets based on Gaussian Filter, Sandipan Chakroborty* and Goutam Saha