Version-2 (Sep-Oct 2016)
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Paper Type | : | Research Paper |
Title | : | Level Converting Retention Flip-Flop for Low Standby Power Using LSSR Technique |
Country | : | India |
Authors | : | Harati V L Devi. Bhupati || M. Lakshmi Prasanna Rani |
ABSTRACT: In VLSI we have an exponential increase of leakage power due to scaling of threshold voltage. We have both active power and standby power dissipation. It is important to reduce standby leakage in case of small battery operated devices. A flip-flop will hold the logic only in the active mode of operation. But a retention flip-flop will hold the data even in the standby mode of operation, with continuously given supply exclusively for the retention latch. A level converting retention flip-flop is used to turn off the voltage regulator in the standby mode of operation..........
Keywords: standby leakage, retention flip-flop, level conversion scheme, forced stack technique, LECTOR & LSSR technique.
[1] Jung-Hyun Park, Heechai Kang, Dong- Hoon Jung, KyunghoRyu, and Seong-Ook Jung "Level – converting Retention Flip-Flop for Reducing Standby Power In ZigBee SOCs" IEEE, 2014.
[2] NamepalliMalathi, B.R.K. Singh. "Multi bit Retention Flip-Flop For ZigbeeSoC's" International Journal of Research in Computer and Communication Technology, Vol 4, Issue 11, November- 2015.
[3] Hamid Mahmoodi-Meimand and Kaushik Roy "Data-Retention Flip-Flops for Power-Down Applications".IEEE, december2008.
[4] Xiaohui Fan, Yangbo Wu, Hengfeng Dong, and Jianping Hu "A low leakage autonomous data retention flip- flop with power gating technique", journal of electrical and computer engineering, 2014.
[5] L. T. Clark, M. Kabir, and J. E. Knudsen, "A low standby power flip-flop with reduced circuit and control complexity," in Proc. IEEE CICC, Sep. 2007, pp. 571–574.
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Paper Type | : | Research Paper |
Title | : | Robust technique of depth focus measure in Wavelet domain |
Country | : | India |
Authors | : | Atika Jain || K.M.Singh || S. Prabhakar Rao |
ABSTRACT: During this paper, we tend to measure a depth focus of image with the assistance of wavelet transform technique. A wavelet based robust technique is to approximate the blurred image mistreatment data carried by the image itself. This blurred image degradation blurs a neighborhood of the data exhibit within the image. The aim of image restoration, is to retrieve this data nearly as good as potential. With Daubechies frequency to high frequency coefficients..........
Keywords: Blurred image, Depth focus measure, Wavelet transform, discrete Wavelet transform
[1] Subbarao, M., Choi, T., Nikzad, A., 1993. Focusing techniques J. Opt. Eng. 32, 2824–2836.
[2] J. Kautsky, J. Flusser, and S. Zitova', "A new wavelet-based measure of image focus," Pattern Recognit. Lett. vol. 23, pp. 1785-1794, 2002.
[3] Jui-Ting Huang, Chun-Hung Shen, See-May Phoong, and Homer Chen, Robust measure of image focus in the wavelet domain. 2005.
[4] Weibao Zou, Yan Li, "Image Classification Using Wavelet Coefficients in Low-pass Bands", IJCNN, Aug 2007.
[5] Shree K. Nayar and Yasuo Nakagawa, "Shape from Focus," IEEE Transactions on Pattern Analysis and Machine Intelligence, vol. 16. No. 8, Aug 1994.
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Paper Type | : | Research Paper |
Title | : | Globally Asynchronous Locally Synchronous (GALS) Microprogrammed Parallel FIR Filter |
Country | : | India |
Authors | : | Gouri Wazurkar || Dr. S. L. Badjate |
ABSTRACT: In thispaper, we propose the design of globallyasynchronouslocallysynchronous (GALS) microprogrammedparallelfinite impulse response (FIR) filterusingpipelined GALS Baugh Wooley Multiplier. The primary objective is to demonstratelow power implementation of microprogrammedparallel GALS FIR filter for digital signal processing applications. Fullysynchronousmicroprogrammedparallel FIR filter and GALS microprogrammed FIR filter are implementedusingsame FPGA and almostsamelogiccells for fairbenchmarking...........
Keywords: Low power, GALS, Microprogrammed, Parallel, FIR Filter.
[1]. Semiconductor Industry Association, "International Technology Roadmap for Semiconductors," http://www.itrs.net.
[2]. L. A. Plana et al., "A GALS infrastructure for a massively parallel multiprocessor," IEEE Design and Test of Computers, vol. 24, no. 5, pp. 454–463, Sep.–Oct. 2007.
[3]. S. Dasgupta and A. Yakovlev, "Comparative analysis of GALS clocking schemes," IET Computer &DigitalTechonolgy, vol. 1, no. 2, pp. 59–69, Mar. 2007.
[4]. Kwen-Siong Chong, et al, "Synchronous-Logic and Globally-Asynchronous-Locally-Synchronous (GALS) Acoustic Digital SignalProcessors", IEEE Journal Of Solid-State Circuits, vol. 47, no. 3, pp 769 – 780, March 2012.
[5]. R.Dobkin, R. Ginosar, and C. P. Sotiriou, "Data synchronization issues in GALS SoCs," in Proc. Int. Symp. Async. Circuits Syst. (ASYNC), pp. 170–179, 2004.
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Paper Type | : | Research Paper |
Title | : | Transient Fault Injection in 4 bit Ripple Carry Adder using Random Sequence Generator |
Country | : | India |
Authors | : | Prof. Vaijayanti H Panse |
ABSTRACT: Fault injection is mainly used to insert a fault in the fault-tolerance based systems. A fault injection technique that enables designers to insert a fault on any signal within the block of a VHDL code is presented. VHDL signals provide the capability to access the values in the code which makes it more testable and observable. The proposed design gives a fault injection system that injects the transient faults in the inputs of a 4 bit ripple carry adder at specific locations..........
Keywords: Fault injection, PN sequence generator, VHDL, Xilinx
[1]. Benso A. and Prinetto P, "Fault Injection Techniques and Tools for Embedded Systems Reliability Evaluation," Kluwer Academic Publishers, Holland, 2003
[2]. Lala Parag K , "Transient and Permanent Fault Injection in VHDL Description of Digital Circuits", Circuits and Systems, 2012, 3, 192-199 http://dx.doi.org/10.4236/cs.2012.32026 Published Online April 2012 (http://www.SciRP.org/journal/cs)
[3]. P. K. Lala, "Self-Checking and Fault Tolerant Digital Design," Morgan Kaufmann Publishers, Waltham, 2001.
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Paper Type | : | Research Paper |
Title | : | A Feature Extraction Scheme to Classify Motor Imagery MovementsBased on Bi-spectrum Analysis of EEG |
Country | : | Bangladesh |
Authors | : | Tonmoy Ghosh || Topu Biswas || Rabeya Khatun |
ABSTRACT: In this paper, an effective but simple feature extraction procedure for motor imagery movement classification has been proposed. Higher-order statistical features are extracted using bi-spectrum analysisof the non-linear EEG signal. Firstly, EEG signals are filtered through a band-pass filter for decomposing EEG signal into several bands and then these signals are bi-spected. Higher-order statistical features i.e. skewness, kurtosis, V2 order, V3 orders, Variance etc. are investigated. From the one-way ANOVA analysis, these features are shown to be promising to distinguish motor imagery hand movement of EEG signals...........
Keywords: Electroencephalogram (EEG); Bi-spectrum; higher order statistics; motor imagery movement
[1] N. Christa, A. Schlgl, and G. Pfurtscheller, Enhancement of left-right sensorimotor EEG differences during feedback-regulated motor imagery, Journal of Clinical Neurophysiology, 16(4), 1999, 373-382.
[2] G. Pfurtscheller and C. Neuper, Motor imagery and direct brain computer communication, Proceedings of the IEEE,89(7),2001, 1123-1134.
[3] E. Niedermeyer and F.H.L. da Silva, Electroencephalography: Basic Principles, Clinical Applications, and Related Fields, Arch Neurol, 40( 3), 1983, 120- 131.
[4] N. Kotoky, S.M. Hazarika, Bispectrum Analysis of EEG for Motor Imagery Classification, Proc.International Conference on Signal Processingand Integrated Networks,2014, 581–586.
[5] C. Schnakers, S. Majerus and S. Laureys, Bispectral Analysis of Electroencephalogram Signals During Recovery from Coma:Preliminary Findings, Neuropsychological Rehabilitation, 15(3), 2005, 381-388.
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Paper Type | : | Research Paper |
Title | : | A New Approach To Real Time Video Denoising using Temporal Video Slicing Frame Synchronization Technique |
Country | : | India |
Authors | : | P.Veeranath || Dr. D.N. Rao || Dr. S.Vathsal |
ABSTRACT: Videos are frequently corrupted by various types of noise either during their process of capturing or during their transmission from one point to another point. In this paper we propose a novel approach for an efficient and improved quality real time video denoising using Temporal Video Slicing and Second generation wavelet transform like Dual tree complex wavelet transform (DTCWT).The Temporal Video Slicing (TVS) technique extracts discrete frames from a noisy video which will undergoes a process by DTCWT framework. The denoised frames are passed to the output instantaneously..........
Keywords: Frame synchronization, Temporal video slicing, Complex wavelet transform and Denoisng
[1] M. G. Bellanger and J. L.Daguet.TDM-FDM transmultiplexer: Digital polyphase and FFT. IEEE Trans. Commun.,22(9):1199.1204,
1974.
[2] R. Calderbank, I. Daubechies, W. Sweldens, and B.-L. Yeo. Wavelet transforms that map integers to integers. Appl.Comput.
Harmon. Anal., 5(3):332.369, 1998.
[3] W. Dahmen, S. Pr¨ossdorf, and R. Schneider. Multiscale methods for pseudo-differential equations on smooth manifolds.In(9),
pages 385.424. 1994.
[4] B.venbkataramini, etc all, "Digital Signal Processing".
[5] Wikipedia "Signal Processing Tutorials.
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Paper Type | : | Research Paper |
Title | : | Implementation of ultra-low power digital circuits using Sub-threshold adiabatic logic |
Country | : | India |
Authors | : | Thakur Priyanka || Dr.K.Ragini |
ABSTRACT: The Energy dissipation in conventional CMOS circuits can be minimized through adiabatic technique and by applying sub-threshold logic. Behavior of adiabatic logic circuits in weak inversion or sub-threshold regime is analyzed in depth to make great improvement in ultra-low power circuit design. In analysis, two logic families, ECRL (Efficient Charge Recovery Logic) and PFAL (Positive Feedback Adiabatic Logic) are compared with conventional CMOS logic for inverter and four bit carry look ahead adder using sub-threshold adiabatic logic. Post layout simulations show that sub-threshold adiabatic units can save significant energy compared with a logically equivalent static CMOS implementation. Results are validated through extensive simulations in 22-nm CMOS technology using TANNER EDA tool.
Keywords: Adiabatic logic, carry look ahead adder (CLA), leakage, low power, sub-threshold.
[1]. Manash Chanda, Sankalp Jain, Student Member, IEEE, Swapnadip De, Member, IEEE, and Chandan Kumar Sarkar, Senior Member, IEEE "Implementation of Subthreshold Adiabatic Logic for Ultralow-Power Application," IEEE transactions on very large scale integration (vlsi) systems, vol. 23, issue:12, dec. 2015.
[2]. J. Kwong, Y. K. Ramadass, N. Verma, and A. P. Chandrakasan, "A 65 nm sub-Vt microcontroller with integrated SRAM and switched capacitor DC-DC converter," IEEE J. Solid-State Circuits, vol. 44, no. 1, pp. 115–126, Jan. 2009.
[3]. T.-T. Liu and J. M. Rabaey, "A 0.25 V 460 nW asynchronous neural signal processor with inherent leakage suppression," IEEE J. Solid-State Circuits, vol. 48, no. 4, pp. 897–906, Apr. 2013.
[4]. A. Calimera, A. Macii, E. Macii, and M. Poncino, "Design techniques and architectures for low-leakage SRAMs," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 59, no. 9, pp. 1992–2007, Sep. 2012.
[5]. H. Soeleman, K. Roy, and B. C. Paul, "Robust subthreshold logic for ultra-low power operation," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 9, no. 1, pp. 90–99, Feb. 2001..
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Paper Type | : | Research Paper |
Title | : | Efficient design and FPGA implementation of JPEG encoder |
Country | : | India |
Authors | : | Krupali M.Lanjewar || R.S.Kawitkar |
ABSTRACT: In this study JPEG standard is used in digital camera which is used to compress the captured image. Hence less space is needed to store the image. Such images are easily shared on the web. Methods/Analysis: Generally, Photos captured from digital camera are big in size, so it takes more time to upload such photos on web. Some time connection speed creates bottle neck on uploading these photos. Best way is to save such photos by .jpg extension and share on the web. Sometimes, while copying the original data, it may not fit in pen drive or memory stick but zip data could easy fit in pen /memory stick. More data one can put in pen drive due to compression. Hence,.........
Keywords: Discrete Cosine Transform (DCT), Field Programmable Gate Array (FPGA), Huffman coding, Joint Photographic Expert Group (JPEG), Quantization.
[1] M. Gangadhar and D. Bhatia, "FPGA based EBCOT architecture for JPEG 2000," Proc. - 2003 IEEE Int. Conf. Field-
Programmable Technol. FPT 2003, vol. 29, pp. 228–233, 2003.
[2] S. Sanjeevannanavar and A. N. Nagamani, "Efficient design and FPGA implementation of JPEG encoder using verilog HDL,"
Proc. Int. Conf. Nanosci. Eng. Technol. ICONSET 2011, pp. 584–588, 2011.
[3] J. Ahmad, "FPGA based implementation of baseline JPEG decoder," no. January, 2009.
[4] "VLSI Implementation of 2-D DCT and Quantization processor for JPEG Image Compression," no. September, 2016.
[5] International Telecommunication Union, "Terminal equipment and protocols for telematic services," Study Gr. VIII, ITU, Geneva,
1988..
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Paper Type | : | Research Paper |
Title | : | Denoising of Rician noise in Magnitude MRI Images using wavelet shrinkage and fusion method |
Country | : | India |
Authors | : | Anjanappa. C || Sheshadri.H.S |
ABSTRACT: Improving the signal-to-noise-ratio (SNR) of magnetic resonance imaging (MRI) using denoising techniques could enhance their value, provided that signal statistics and image resolution are not compromised. Here, a new denoising method based on wavelet based bayes shrinkage method of the measured noise power from each signal acquisition is presented. Bayes shrink method denoising assumes no prior knowledge of the acquired signal and does not increase acquisition time. Whereas conventional denoising/filtering methods are compromised in parallel imaging by spatially dependent noise statistics, wavelet based method is performed on signals acquired from MRI. Using numerical simulations..........
Keywords: Haar transform, db3 transform, Bayes shrinkage, Fusion technique.
[1] Benjamin Y.M.Kwan " Impulse Noise Reduction in Brain Magnetic Resonance Imaging using Fuzzy Filters" World Academy of Science, Engineering and Technology 2011.
[2] Abdullah Toprak "Impulse noise reduction in medical images with the use of switch mode fuzzy adaptive median filter" Digital signal vol. 17, pp no.711-723. 2007
[3] Oshinskiet al.: Cardiovascular magnetic resonance at 3.0T: Current state of the art journal of Cardiovascular Magnetic Resonance 2010doi:10.1186/1532-429X-12-55.
[4] 4.Lin Xu, Changqing Wang, Wufan Chen, and Xiaoyun Liu,"Denoising Multi-Channel Images in Parallel MRI by Low Rank Matrix Decomposition" IEEE transaction on applied superconductivity vol. 24, no. 5, October. 2014
[5] Anagha Deshmane, MEng, Vikas Gulani, MD, PhD, "Parallel MR imaging" Journal of Magnetic Resonance Imaging Vol. 36,pp.55–72, 2012.
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Paper Type | : | Research Paper |
Title | : | Non Linear Prediction Based Speech Coder using FTRLS Algorithm |
Country | : | India |
Authors | : | Mithun M S || Ancy S Anselam |
ABSTRACT: The purpose of this contribution is to present a new approach for the prediction of speech signals that is appropriate to speech coding. Linear predictive coding is probably the most frequently used technique in speech signal processing. Since its neglects nonlinear effects during the speech production process, some adaptive techniques are used to make the system nonlinear to perform better than linear techniques, enabling better performance in a number of speech processing applications. Also adaptive techniques with nonlinear prediction of speech based on truncatedVolterra series is used..........
Keywords: Nonlinear speech processing, Pitch period, Prediction, Volterra series, Adaptive Filters, RLS, least-squares.
[1]. Vladimir Despotović and Zoran Perić, "Design of Nonlinear Predictors for Adaptive Predictive Coding of Speech Signals," in 21st Telecommunications forum TELFOR 2013 Serbia, Belgrade, November 26-28, 2013.
[2]. V. Despotovic, N. Goertz and Z. Peric, "Nonlinear long-term prediction of speech based on truncated Volterra series," IEEE Transactions on Audio, Speech and Language Processing, vol. 20, no. 3, pp. 1069-1073, 2012.
[3]. Dan J. Dechene, "Fast Transversal Recursive least-squares (FT-RLS) Algorithm," in Department of Electrical and Computer Engineering University of Western Ontario. [4]. S. Haykin, Adaptive Filter Theory, 4th ed. Pearson Education, 2002.
[2] P. S. R. Diniz, Adaptive Filtering: Algorithms and Practical Implementation. Kluwer Academic Publishers, 1997.
[5]. V. Despotovic, N. Goertz and Z. Peric, "Low-Order VolterraLongTerm Predictors," in Proc. 10th ITG Symposium on Speech Communication, Braunschweig, Germany, Sept. 2012, pp. 26-28.