iosr-JVSP   Volume-4 ~ Issue-2 ~ March-April 2014

ABSTRACT: A new method of classifying satellite images into different categories such as forest, desert, river etc., with the help of Support Vector Machine (SVM) and unsupervised learning method using MATLAB is presented. Dense low-level feature descriptors are extracted and exploited in a novel way to learn a set of basis functions. The low-level feature descriptors are encoded in terms of the basis functions to generate new sparse representation for the feature descriptors. We pool these sparse features by simple averaging and show that this method will help us to choose SVM classifier which is having less cost. Experimental results show its good performance, when tested with different saliency criteria, such as accuracy, less computational time, and the combination of both

[1] Y.Yang and S. Newsam, "Bag-of-visual-words and spatial extensions for land-use classification," in Proc. ACM Int. Conf. Adv. Geogr. Inf. Syst.,2010, pp. 270–279.
[2] J. Wright, Y. Ma, J. Mairal, G. Sapiro, T. S. Huang, and Y. Shuicheng, "Sparse representation for computer vision and pattern recognition,"Proc. IEEE, vol. 98, no. 6, pp. 1031–1044, Jun. 2010.
[3] Y.-L. Boureau, F. Bach, Y. LeCun, and J. Ponce, "Learning mid-level features for recognition," in Proc. IEEE Conf. Comput. Vis. Pattern Recognit., 2010, pp. 2559–2566.
[4] S. Lazebnik, C. Schmid, and J. Ponce, "Beyond bags of features: Spatial pyramid matching for recognizing natural scene categories," inProc. IEEE Conf. Comput. Vis. Pattern Recognit., 2006, vol. 2, pp. 2169–2178.
[5] Y. Yang and S. Newsam, "Spatial pyramid co-occurrence for image clas-sification," inProc. IEEE ICCV, Nov. 2011, pp. 1465–1472.

ABSTRACT:Quantum dot Cellular Automata (QCA) is the new possibility for the future of nano-electronic computing technology which employs the principle of quantum mechanics. This paper, contributes to the design of Memory circuits based on conservative reversible logic gates & also the design is made testable using two test vectors. The conservative logic gates dominates the classical gates in terms of testability, feature size scaling & high power consumption for the design of sequential circuits. Here the Memory circuits (1-bit, 4-bit & 8-bit) are designed by employing conservative logic gates(Fredkin Gate), which is being simulated and tested for the detection of unidirectional stuck-at faults using two test vectors 0s & 1s. For the simulation of the described designs Xilinx's 8.2 EDA tool is used.
Keywords: conservative reversible logic, Fredkin gate, QCA, stuck-at-faults, memory

[1] J. Ren and V. K. Semenov, "Progress with physically and logically reversible superconducting digital circuits," IEEE Trans. Appl. Super- conduct., vol. 21, no. 3, pp. 780-786, Jun. 2011.
[2] S. F. Murphy, M. Ottavi, M. Frank, and E. DeBenedictis, "On the design of reversible QDCA systems," Sandia National Laboratories, Albuquerque, NM, Tech. Rep. SAND2006-5990, 2006.
[3] H. Thapliyal and N. Ranganathan, "Reversible logic-based concurrently testable latches for molecular QCA, " IEEE Trans. Nanotechnol., vol. 9, no. 1, pp. 62-69, Jan. 2010.
[4] P. Tougaw and C. Lent, "Logical devices implemented using quantum cellular automata," J. Appl. Phys., vol. 75, no. 3, pp. 1818-1825, Nov. 1994.
[5] P. Tougaw and C. Lent, "Dynamic behavior of quantum cellular automata," J. Appl. Phys., vol. 80, no. 8, pp. 4722-4736, Oct. 1996.

ABSTRACT: The need for extra elements for coupling will add noise and increase power dissipation to the LC-QVCOs. To improve the phase noise, various experiments are done to modify the coupling networks. A new clock gated quadrature voltage-controlled oscillator (QVCO) using differential Colpitts oscillator is presented. The coupling technique presented is applicable to N differential Colpitts QVCOs for multiphase signals generation and a clock gated multiphase QVCO is presented. The main advantage of this technique is that, here we are not using any coupling networks. The clock gated QVCO is combined of two similar current-switching differential Colpitts VCOs in which the first core VCO is connected to the second in an in-phase manner, and the second core VCO is connected to the first in an anti-phase manner. For this connection the substrates of the interconnected transistors as well as the substrates of MOS varactors are used. A linear (sinusoidal) analysis is showed that verify that the VCO circuit generates quadrature waveforms.
Keywords: quadrature oscillator, low-phase noise, multiphase, Current-switching Colpitts-oscillator.

[1] Andreani .A, Bonfanti. A, Romano. L, and Samori.C,(2002)Analysis and design of 1.8 GHz CMOS LC quadrature oscillator‟ IEEE J. Solidtate
Circuits, vol. 37, no. 12, pp. 1737-1747. 2
[2] Aparicio .Rand Hajimiri.A,(2002) "A noise-shifting differential. Colpitts VCO,‟ IEEE J. Solid-State Circuits, vol. 37, no. 12, 4
[3] Chu.Mand Allstot.D,J, (2004) "A 6 GHz low-noise quadrature Colpitts VCO,‟ in Proc. IEEE Int. Conf. Electron., Circuits Syst. 6
[4] Chuang.Y.H, Lee.C.K, and Lee.S.H, (2006) "A 4.8GHzLow phase noise quadrature ColpittsVCO,‟ presented at the Int. Symp.VLSI Design,
Autom., Test, Hsinchu, Taiwan. 5
[5] Ebrahimi.E and Naseh.S, (2011)"A new robust capacitively coupled second harmonic quadrature LC oscillator,‟AnalogIntegr. Circuits
SignalProcess., vol. 66, no. 2, pp. 269–275. 14.

ABSTRACT: Low power came in to limelight in the current generation of electronic design. Earlier area and performance and cost were the priority of design engineers overlooking power. However trade off exist between area, performance and power. Overall performance of the circuit is affected by its components. Optimization of the design is accomplished by compromising design issues and components. With the shrinking technology below 90 nm power dissipation and its management has been critical for designer .Importance for optimization has been drawn from extended battery life and lowering package cost. This paper presents a literature review upon the strategies and methodologies in designing low power VLSI circuits.
Keywords: VLSI circuits, Low power management, Low power strategies, power dissipation, Power optimization.

[1] Zamin Ali Khana ,S. M. AqilBurneyb, , Jawed Naseemc, KashifRizwand, "Optimization of Power Consumption in VLSI Circuit" IJCSI International Journal of Computer Science Issues, Vol. 8, Issue 2, March 2011
[2] KanikaKaur, Arti Noor, "STRATEGIES & METHODOLOGIES FOR LOW POWER VLSI DESIGNS: A REVIEW" ,International Journal of Advances in Engineering & Technology, May 2011.
[3] Dr. Neelam R, Prakash, Akash, "Clock Gating for Dynamic Power Reduction in Synchronous Circuits" ,International Journal of Engineering Trends and Technology (IJETT) – Volume4Issue5- May 2013.
[4] BagadiMadhavi, G Kanchana, VenkateshSeerapu, "Low Power and Area Efficient Design of VLSI Circuits" ,International Journal of Scientific and Research Publications, Volume 3, Issue 4, April 2013
[5] Sherif A. Tawfik and VolkanKursun,"Low Power and High Speed Multi Threshold Voltage Interface Circuits",IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS.

ABSTRACT:In the field of Image processing there are many techniques to detect edges. Some of the methods are 'First derivative method' ,'Second derivative method', Sobel, Laplacian of Guassian(LoG) and these methods are used for image segmentation and object identification. In this paper, a novel idea on how to detect edges using MATLAB has been described. The edges have been detected using fuzzy logic and image processing tool boxes. A novel method of detecting edges through Artificial Neural Networks(ANN) has been proposed. Experimentation is performed on gray scale image in MATLAB using First derivative, second derivative and Sobel operator.

[1]. ZahariDoychev, edge detection and feature extraction
[2]. Mohamed A. El-Sayed, A New Algorithm Based Entropic Threshold for Edge Detection in Images [3]. You-yiZheng, Ji-laiRao, Lei Wu, "Edge detection methods in digital image processing, "Computer Science and Education (ICCSE), 2010 5th International Conference", page 471 – 473 on Aug. 2010 ,Ferdinand van der Heijden, Edge and Line Feature Extraction Based on Covariance Models
[4]. Gonzalez woods and Eddins, Digital image processing

ABSTRACT:Content addressable memory (CAM) is a memory that implements the look up table function in a single clock cycle using dedicated comparison circuitry. CAM's are composed of conventional semiconductor memory (usually SRAM) with added comparison circuitry that enables a search operation to complete in a single clock cycle. Content addressable memory offers high-speed search function in a single clock cycle. Due to its parallel match-line (ML) comparison, CAM is power-hungry

[1]. Anh-Tuan Do, Shoushun Chen, Zhi-Hui Kong, and KiatSeng Yeo,(2013),"A High Speed Low Power CAM With a Parity Bit and Power-Gated ML Sensing,‟ IEEE Transactions On Very Large Scale Integration (VLSI) Systems, Volume. 21, No. 1, pp. 151-156.
[2]. Arsovski. I and Sheikholeslami. A,(2003),"A mismatch-dependent power allocation technique for match-line sensing in content-addressable memories,‟ IEEE J. Solid-State Circuits, Volume. 38, No. 11, pp. 1958–1966.
[3]. Do.A.T, Chen.S.S, Kong.Z.H and Yeo.K.S,(2011),"A low-power CAM with efficient power and delay trade-off,‟ in Proc. IEEE Int. Symposium CircuitsSystem (ISCAS), pp. 2573–2576.
[4]. Igor Arsovski, Trevis Chandler, A. Sheikholeslami,(2003),"A ternary content-addressable memory (TCAM) based on static storage and including a current- race sensing scheme‟, IEEE J. Solid-State Circuits, Volume. 38.
[5]. Jose. G. Delgado and JabulaniNyathi,(2000),"A VLSI High-Performance Encoder with Priority Lookahead‟, IEEE Transactions on Computers, Volume. 30, No. 5, pp 565-570.
[6]. Mohan.N, Fung.W, Wright.D and Sachdev.M,(2009),"A low-power ternary CAM with positive-feedback match-line sense amplifiers,‟ IEEE Trans. Circuits Syst. I, Reg. Papers, Volume. 56, No. 3, pp. 566–573.

ABSTRACT:Today, there is a large demand for portable electronics for computing and communication. In order to satisfy these requirements, we are focusing on low voltage design techniques. If we reduce the Supply voltage, we also have to reduce the Threshold voltage to maintain the performance. If we reduce the Threshold voltage to lower values, the leakage current cannot be neglected. The leakage power is dependent on the input vector control. This leakage power will get dissipated even when the gates are in ideal condition. We propose a Novel technique. This technique uses a integer linear programming(ILP) model.

[1]. "Leakage power estimation & minimization in VLSI Circuits" by Wen-Tsong Shine.
[2]. "Four –Bit Cmos Full Adder Design in Submicron Technology with Low Leakage Power & Ground Bounce Noise Reduction using Dual Sleep Approach" by Y.Jagadeesh,T.Krishnamurthy.
[3]. "Standby and Active Leakage Current Control & Minimizaion in CMOS VLSI Circuits" by Farzan Fallah,Massoud Pedram.
[4]. "Studying Impact of Various Leakage Current Reduction Techniques on Different D-Flipflop Architectures" by UdaiyaKumar.R,Anbarasu.W.
[5]. "Off-State Leakage Power Reduction by Automatic Monitoring & Control System" by S.Abdollahi Pour & M.Saneei.

ABSTRACT:Processors for next generation mobile devices will need to operate across a wide supply voltage range in order to support both high performance and high power efficiency modes of operation. However, the effects of local transistor threshold variation, already a significant issue in today's advanced Process technologies, and further exacerbated at low voltages, complicate the task of designing reliable, manufacturable systems for ultra-low voltage operation. In this paper, we describe a 4-issue VLIW DSP system-on-chip (SoC), which operates at voltages from 1.0 V down to 0.6 V. The SoC was implemented in 28 nm CMOS, using a cell library and SRAMs optimized for both high-speed and low-voltage operating points.

[1] B. H. Calhoun and A. Chandrakasan, "Characterizing and modelingminimum energy operation for subthreshold circuits," in Proc.ISLPED, 2004, pp. 90–95.

[2] B. Cheng, D. Dideban, N. Moezi, C. Miller, G. Roy, X. Wang, S. Roy,and A. Asenov, "Benchmarking statistical compact modeling strategies for capturing device intrinsic parameter fluctuations in BSIM4 and PSP," IEEE Design and Test of Computers, vol. 27, no. 2, pp. 26–35, Mar. 2010.

[3] J. Kwong and A. Chandrakasan, "Variation-driven device sizing forminimum energy sub-threshold circuits," in Proc. ISLPED, 2006, pp.8–13.

[4] H. Nho, P. Kolar, F. Hamzaoglu, Y. Wang, E. Karl, N. Yong-Gee, U.Bhattacharya, and K. Zhang, "A 32 nm high- metal gate SRAM with adaptive dynamic stability enhancement for low-voltage operation," inIEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2010,pp. 346–347.

ABSTRACT: Any integrated system consists of a host processor, memory and peripheral elements which are interconnected through a bus interface. The synchronization of these basic blocks with internal and external environment is achieved by means of an I/O buffer. The work is intended to develop a self-reconfigurable channel data buffering form and circuit design for network-on-chips (NoCs). The design is optimized for power efficiency and data throughput, from system to circuit level.

[1] Everton Carara, Ney Calazans, Fernando Moraes; Journal Integrated Circuits and Systems 2008; v.3 , "A New Router Architecture for High-Performance Intrachip Network"
[2] Sheraz Anjum, Ehsan Ullah Munir,Waqas Anwar and Nadeem Javaid, Research Journal of Applied Sciences, Engineering and Technology 5(2): 353-356, 2013, "Object Oriented Model for Evaluation of On-Chip Networks"
[3] Boris Grot, Joel Hestness, Stephen W. Keckler, Onur Mutlu. Computer Architecture (ISCA), 2011 38th Annual International, Symposium on Publication Year: 2011, "Kilo-NOC: A Heterogeneous Network-on-Chip Architecture for Scalability and Service Guarantees"
[4] Partha Pratim Pande, Cristian Grecu, Michael Jones, André Ivanov, Resve Saleh, August 2005 (vol. 54 no. 8) pp. 1025-1040 , "Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures" [5] Wan-Ting Su ; Comput. Sci. & Inf. Eng., Nat. Chung Cheng Univ., Chiayi, Taiwan ; Jih-Sheng Shen ; Pao-Ann Hsiung, Automation Conference (ASP-DAC), 2011 , "Network on chip router design with buffer stealing" [6] Kumar, S. ; Lab. of Electron. & Comput. Syst., R. Inst. of Technol., Stockholm, Sweden ; Jantsch, A. ; Soininen, J.-P. ,IEEE Computer Society Ann Publiched date 24 April 2014ual Symposium on VLSI,2002, " A network on chip architecture and design methodology"

ABSTRACT: VLSI technology has developed over the years thereby enhancing the performance of chips in terms of three basic constraints viz. delay, power and area. Gate Diffusion Input technique is one such method which attempts to minimize the delay and power consumed by the circuit. The paper basically focuses on the implementation of the technique on combinational logic circuits and experimental delay results have been produced and these results have been compared with the conventional CMOS logic showing a reduction in delay and power-delay product using GDI. The graphical plots of digital circuits showing their transient behavior have also been presented.

[1] Arkadiy Morgenshtein, Alexander Fish, and Israel A. Wagner, Gate-Diffusion Input (GDI: A Power-Efficient Method for Digital Combinatorial Circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 10 (5), OCTOBER, 2002.

[2] J. P. Uyemura, Circuit Design for CMOS VLSI (Norwell, MA: Kluwer Academic, 1992, pp. 88–129).

[3] N. Weste and K. Eshraghian, Principles of CMOS digital design (Reading, MA: Addison-Wesley, pp. 304–307).

[4] A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, Low- power CMOS digital design, IEEE J. Solid-State Circuits, vol. 27, Apr. 1992.

[5] V. Adler and E. G. Friedman, Delay and power expressions for a CMOS inverter driving a resistive-capacitive load,Analog Integrat. Circuits Signal Procesing., 14, pp. 29–39, 1997.

[6] Amit Rathi and Ritu Vijay, Optimization of MSA with Swift Particle Swarm Optimization, International Journal of Computer Application(IJCA), 8, December 2010, pp. 28-33.

ABSTRACT: Resolution enhancement (RE) schemes suffer from the drawback of losing high frequency contents (which results in blurring). The wavelet-transform-based RE scheme, generates artifacts (due to a shift-variant property). Therefore a framelet-domain approach and non-local means (NLM) filter is proposed for RE of the satellite images. A satellite input image is decomposed by Framelet transform ( FT) to obtain high-frequency subbands. The high-frequency subbands and the low-resolution (LR) input image are interpolated using the Lanczos interpolator. The high frequency subbands are passed through an NLM (despite of its nearly shift invariance). The filtered high-frequency subbands and the LR input image are combined using inverse FT to obtain a resolution-enhanced image. Objective and subjective analyses reveal superiority of the proposed technique over the RE techniques.
Keywords: Framelet Transform, Wavelet Transforms, Resolution Enhancement, Lanczos Interpolator, Shift variant

[1] Y. Piao, I. Shin, and H. W. Park, "Image resolution enhancement using inter- Subband correlation in wavelet domain," 2007
[2] C. B. Atkins, C. A. Bouman, and J. P. Allebach, "Optimal image scaling using pixel classification," Oct. 7–10, 2001
[3] H. Demirel and G. Anbarjafari, "Satellite image resolution enhancement using complex wavelet transform," IEEE Jan. 2010.
[4] H. Demirel and G. Anbarjafari, "Discrete wavelet transform-based satellite image resolution enhancement,"IEEEJun. 2011.
[5] H. Demirel and G. Anbarjafari, "Image resolution enhancement by using discrete and stationary wavelet decomposition," IEEE May 2011.

ABSTRACT: A high-speed and energy-efficient multiplier is always required in electronics industry particularly in digital signal processing, arithmetic units in microprocessor and image processing. Multiplier is a significant element which contributes to the total power utilization of the system. By comparing different types of adders it is found that the ripple carry adder has a smaller area with lesser speed performance, in contrast to which carry select adders have high speed but posses a larger area. In the existing models of the multipliers, the regular square root carry select adder and modified square root carry select adder using Binary to Excess-1 logic are designed and implemented on both Array and Wallace tree multipliers respectively. In the proposed work a proficient square root carry select adder is designed using common Boolean logic and is implemented on both Array and Wallace tree multipliers respectively. A well-organized Verilog code has been written and successfully synthesized and simulated using Xilinx ISE 14.2. The simulation results gives the performance of Array and Wallace tree multipliers using proposed square root carry select adder is excellent compared with other structures of square root carry select adders.
Keywords: Array Multiplier, Wallace Tree Multiplier, Square Root Carry Select Adder, Binary to Excess-1 Converter (BEC), Common Boolean Logic (CBL).

[1] B. Ramkumar and Harish M Kittur, "Low power and area efficient carry select adder", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, no. 2, pp. 371-375, Feb 2012.
[2] Damarla Paradhasaradhi and K. Anusudha, "An Area Efficient Enhanced SQRT Carry Select Adder", International Journal of Engineering Research and Applications, vol. 3, Issue 6, Nov-Dec 2013.
[3] Jasbir Kaur and Kavita, " Structural VHDL Implementation of Wallace Multiplier", International Journal of Scientific & Engineering Research, vol. 4, Issue. 4, pp. 1829-1833, April 2013.
[4] N. Sureka, R. Porselvi and K. Kumuthapriya, "An efficient high speed Wallace tree Multiplier", Proceedings of IEEE International Conference on Information Communication and Embedded Systems, pp. 1023-1026, Feb 2013.
[5] Naveen K Gahlan, Prabhat, Jasbir Kaur " Implementation of Wallace Tree Multiplier Using Compressor" International Journal of Computer & Technology.