iosr-JVSP   Volume-5 ~ Issue-4 ~ July-August 2015

ABSTRACT: Increase in multimedia applications drastically increased the demand for digital information. Reduction in the size of this data for transmission and storage is very important. This is done by Image compression. JPEG (Joint Photographic Experts Group) is an international compression standard for continuous-tone still image, both grayscale and color. There are software solutions as well as hardware solutions for JPEG compression depending upon the application. Hardware solutions are mainly used for high speed and parallel processing applications. As the distinct requirement for each of the applications, the JPEG standard has two basic compression methods.

[1]. Digital Integrated Circuits A Design Perspective 2nd Ed- Rabey
[2]. A Low Area Pipelined 2-D DCT Architecture for JPEG Encoder by Qihui Zhang, Nan Meng
[3]. D. Trang, N. Bihn, "A High-Accuracy and High-Speed 2-D 8x8 Discrete Cosine Transform Design". Proceedings of ICGC-RCICT 2010, vol. 1, 2010, pp. 135-138
[4]. Pipelined Fast 2-D DCT Architecture for JPEG Image Compression by Lucian0 Volcan Agostini, Ivan Saraiva Silva, Sergio Bampi
[5]. Parallel-Pipeline 8 8 Forward 2-D ICT Processor Chip for Image CodingGustavo A. Ruiz, Juan A. Michell, and Angel M. Burón

ABSTRACT:In this paper, a new approach for 2-D DCT architecture is introduced where both area and power are improved simultaneously. To reduce the area the proposed architecture is designed with tristate buffers. It can calculate first-dimensional and second-dimensional transformations simultaneously by using 1-D discrete cosine transform (DCT) core to reach less hardware utilization. Modules in the 1-D DCT core, including the modified two-input butterfly (MBF2), the pre-reorder, the process element even (PEE), the process element odd (PEO), and the post reorder are designed using the VERILOG HDL.

[1]. A. M. Shams, A. Chidanandan , W. Pan, and M. A. Bayoumi, "NEDA: A low-power high performance DCT architecture," IEEE Trans. Signal Process., vol. 54, no. 3, pp. 955–964, Mar. 2006.
[2]. A. Madisetti and A. N. Willson , "A 100 MHz 2-D 8 X 8 DCT/IDCT processor for HDTV applications," IEEE Trans. Circuits Syst. Video Technol., vol. 5, no. 2, pp. 158–165, Apr. 1995.
[3]. A. Tumeo, M. Monchiero, G. Palermo, F. Ferrandi, and D. Sciuto, "A pipelined fast 2DDCTaccelerator for FPGA-based SOCs," in Proc. IEEE Comput. Soc. Annu. Symp. VLSI., 2007, pp. 331– 336.
[4]. C. C. Sun, P. Donner, and J. Gotze, "Low complexity multi-purpose IP core for quantized discrete cosine and integer transform," in Proc. IEEE Int. Symp. Circuits Syst.,2009, pp. 3014–3017.
[5]. C. Peng , X. Cao, D. Yu, and X. Zhang, "A 250 MHz optimized distributed architecture of 2D 8 x 8 DCT," in Proc. Int. Conf. ASIC, 2007, pp. 189–192.

ABSTRACT: Underwater photography is challenging due to poor illumination and varying environment condition. Due to the insufficient illumination provided by the Automated Underwater Vehicles (AUV), the obtained degraded images need to be enhanced. Image enhancement techniques have to be implemented in hardware to be used with AUVs. Field Programmable Gate Arrays (FPGA) have been proved to be a better option for being used in image processing techniques due to it's inherit parallelism.

[1]. Retrieved from : http://www.bbc.co.uk/history/ancient/archaeology/marine_01.shtml
[2]. Erhardt – Ferron ;Theory and Applications of Digital Image Processing university Of Applied sciences of fenburg hochschule for technik undwirt schaft
[3]. Beilei Xu; Yiqi Zhuang; Hualian Tang; Li Zhang, "Object-based multilevel contrast stretching method for image enhancement," Consumer Electronics, IEEE Transactions on , vol.56, no.3, pp.1746,1754, Aug. 2010.
[4]. Kim, Tae Keun, Joon Ki Paik. and Bong Soon Kang. Contrast enhancement system using spatially adaptive histogram equalization with temporal filtering. Consurner Electronics, IEEE Transactions on 44, no. I (1998): 82-87
[5]. Jiang Duan; Wenpeng Dong; Rui Mu; Guoping Qiu; Min Chen, "Local contrast stretch based tone mapping for high dynamic range images," Computational Intelligence for Multimedia, Signal and Vision Processing (CIMSIVP), 2011 IEEE Symposium on , vol., no., pp.26,32, 11-15 April 2011
[6]. Eramian, M.; Mould, D., "Histogram equalization using neighborhood metrics," Computer and Robot Vision, 2005. Proceedings. The 2nd Canadian Conference on , vol., no., pp.397,404, 9-11 May 2005

ABSTRACT: This paper presents the performance analysis between two different Phase Frequency Detector approaches with Charge Pump. The Phase Frequency Detector (PFD) is an important building block of phase locked loop (PLL). The conventional and modified architecture of phase frequency detector with charge pump are compared in terms of area and power consumption. The phase frequency detector and charge pump are designed and simulated using Cadence tool in GPDK 180nm technology. The modified phase frequency detector has either UP or DOWN signals at a time. The conventional PFD also has one output either UP or DOWN at a time. The charge pump varies VCONTROL voltage according to the UP or DOWN signal which in turn controls frequency of voltage controlled oscillator (VCO).

Keywords: Charge Pump, Loop Filter, PFD, PLL, VCO.

[1]. Md Monirul Islam; Ankit Shivhare, "The design of a low power floating gate based phase frequency detector and charge pump implementation," International Journal of VLSI design & Communication Systems (VLSICS), Vol.4, No.2, April 2013.
[2]. Kailuke, A.C.; Agrawal, P.; Kshirsagar, R.V., "Design of Phase Frequency Detector and Charge Pump for Low Voltage High Frequency PLL," Electronic Systems, Signal Processing and Computing Technologies (ICESC), 2014 International Conference on , vol., no., pp.74,78, 9-11 Jan. 2014
[3]. Majeed, K.K.A.; Kailath, B.J., "Low power, high frequency, free dead zone PFD for a PLL design," Faible Tension Faible Consommation (FTFC), 2013 IEEE , vol., no., pp.1,4, 20-21 June 2013
[4]. Sreehari, P.; Devulapalli, P.; Kewale, D.; Asbe, O.; Krishna Prasad, K.S.R., "Power optimized PLL implementation in 180nm CMOS technology," VLSI Design and Test, 18th International Symposium on , vol., no., pp.1,2, 16-18 July 2014.

ABSTRACT: The demand for low power devices is increasing vastly due to the fast growth of battery operated applications such as smart phones and other handheld devices. It has become important to control the power dissipation throughout the design cycle beginning from the architectural level to final design at hardware level. Leakage current is the main factor which contributes to almost or more than 50% of total power dissipation. In many new high performance designs, the leakage component of power consumption is comparable to the switching component. More than 40% leakage in SRAM memory is due to leakage in transistors. This survey paper use the design of SRAM architecture to reduce the leakage current and hence the leakage power.

[1]. E. Seevinck, F. List, and J. Lohstroh, "Static-noise margin analysis of MOS SRAM cells," IEEE J. Solid-State Circuits, vol.SC-22, no.5; pp.748-754, Oct.1987.
[2]. Vikas Nehra, Rajesh Singh, Neeraj Kumar Shukla, Shilpi Birla, Mahima Kumar, Ankit Goel, "Simulation & Analysis of 8T SRAM Cell‟s Stability as Deep Sub-Micron CMOS Technology for Multimedia Applications," Canadian Journal on Electrical and Electronics Engineering Vol. 3, No.1, January 2012.
[3]. Yih Wang, Hong Jo Ahn, Uddalak Bhattacharya, Zhanping Chen, Tom Coan, Fatih Hamzaoglu, Walid M.Hafez, Chia-Hong Jan, Pramod Kolar, Sarvesh H. Kulkarni, Jie-Feng Lin, Yong-Gee Ng, lan Post, Liqiong Wei, Ying Zhang, Kevin Zhang, and Mark Bohr, "A 1.1 Ghz 12u A/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications," IEEE Journal of Solid-State Circuits, Vol. 43, No. 1, January 2008.

ABSTRACT:A conventional Full Adder using 28 transistors is presented here. In digital signal processors and microprocessors, the Full Adder is not only important for addition based digital circuit like multiplier and divider but is also used for accessing the address in memory. For low power requirement, there is a need to reduce leakage current in Full Adder. In this paper SVL (self controllable voltage level) technique is introduced for leakage current reduction and then standby leakage power reduction. Using SVL technique we can provide DC voltage supply as per requirement for load circuit in active mode and decrease DC voltage supply for load circuit in standby mode.

[1]. Garg, D., Rai, M. K. 2012. CMOS Based One Bit Full Adder Cell for Low Power Delay Product. IJECCT. vol. 2, issue. 4, pp. 18-23.
[2]. Wairya, S., Nagaria, R.K., Tiwari, S. 2012. Comparative Performance Analysis of XOR XNOR Function Based High Speed Cmos Full Adder Circuits for Low Voltage VLSI Design. International Journal of VLSI Design and Communication System. vol. 3, No.2, pp. 221-242.
[3]. Reddy, P. P. K., Satyanarayana, K. V. 2014. Power Analysis of Different Full Adder With different CMOS Logic Design. International journal of Engineering Trends and Technolgy. Vol. 16.
[4]. Channegowda, .C, Dr. Aswatha, A. R. 2013. Low Power One Bit Full Adder Cell Using Modified Pass Transistor Logic. International Journal of Computer Science and Information Technologies. Vol.4, No.3, pp. 489-491.
[5]. Suresh, G., Rao, C. S. 2014. Performance Evaluation of Full Adder And its Impact on Ripple Carry Design. International Journal of Research in Engineering and Technology. Vol. 3, No. 4, pp. 23-28.

ABSTRACT:In microprocessor and digital signal processor, Full Adder performs addition and therefore it is used for arithmetic operation and is also used for comparison and access the address in memory. For highly efficient operation of low powered and battery operated portable devices, Full adder is implemented using different structures. There is a 1-bit full adder using10 transistors are proposed in this paper. There are two techniques 1) power gating technique and 2) SVL (switch controllable voltage level) technique are proposed for reducing leakage current. The results based on power gating technique and SVL technique show that leakage current of
10 transistors based1-bit Full Adder are reduced to a large extent.

[1]. Deepak Garg, Mayank Kumar Rai. 2012. CMOS Based One Bit Full Adder Cell for Low Power Delay Product. IJECCT. vol. 2,
issue. 4, pp. 18-23.
[2]. Subodh Wairya, Rajendra Kumar Nagaria, sudarshan tiwari. 2012. Comparative Performance Analysis of XOR XNOR Function
Based High Speed Cmos Full Adder Circuits for Low Voltage VLSI Design. International Journal of VLSI Design and
Communication System. vol. 3, No.2, pp. 221-242.
[3]. Richa Saraswat, Shyam Akashe and Shyam Babu Designing and Simulation of Full Adder Cell Using FINFET Technique in
Proceedings of 7th International Conference on Intelligent Systems and Control (ISCO),2013 pp. 261-264.
[4]. Suresh, G., Rao, C. S. 2014. Performance Evaluation of Full Adder And its Impact on Ripple Carry Design. International Journal
of Research in Engineering and Technology. Vol. 3, No. 4, pp. 23-28.

ABSTRACT: Low power has emerged as a principal theme in today's electronics industry. Over the past decade, the power consumption of VLSI chips has constantly been increasing. In Integrated Circuit, there is a need of data to communicate among logic gates using flip-flop (FF). In a FF, a huge portion of the on-chip power is consumed by clock systems, which consists of timing elements such as FFs, latches and clock distribution network. These components consume 30% to 60% of the total power in a system. So to reduce Power dissipation, various conventional methods are implemented using TSPC but there is a discharging path problem.

[1]. Vladimir Stojanovic and Vojin G. Oklobdzija, "Comparative analysis of master slave latches and filp flops for high performance and low power systems," IEEE Journal of Solid-State Circuits, vol. 34, no. 4, April 1999, pp.536-548.
[2]. S.P.Loga priya, P.Hemalatha, "Design and Analysis of low power pulse triggered flip flop," International Journal of Scientific and Research Publications, Volume 3, Issue-4, April 2013, ISSN: 2250-3153.
[3]. Jiren Yuan and Christer Svensson, "New Single Clock CMOS Latches and Flip Flops with Improved Speed and Power Saving," IEEE Journal of Solid State Circuits, vol.32, no.1, Jan 1997, pp. 62-69.
[4]. Hong-Yi Huang, 'Kuo-Hsing Cheng, Jim-Shyan Wang, Yuan-Hua Chu, Vain-Shun Wu, and Clung-Yu Wu, " Low voltage low power CMOS true single-phase clocking scheme with locally asynchronous logic circuits," IEEE Xplore, pp. 1572-1575.
[5]. Yin-Tsung Hwang, Jin-Fa Lin, and Ming-Hwa Sheu, "Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, no.2, Feb. 2012, pp.361-366.

ABSTRACT: Multi processor system on chip (MPSOC) has been consider as the best candidate for applications such as networking, telecommunication, multimedia, etc. which have need of high computational demand, high performance, flexibility, high energy efficiency and low cost design. Multistage switching networks are best suited for applications which use large number of parallel systems and memories.MPSOCS are well associated with switching networks to perform variety of scientific applications and parallel processing.

[1]. Wayne Wolf, Fellow, IEEE, Ahmed Amine Jerraya, and Grant Martin, Senior Member, IEEE, ―Multiprocessor System-on-Chip (MPSoC) Technology‖ IEEE transactions on computer-aided design of integrated circuits and systems, vol. 27, no. 10, october 2008.
[2]. Lionel Torres, Pascal Benoit, Gilles Sassatelli, Michel Robert University Of Montpellier LirmmUmrCnrs, France Diego Puschini, Fabien ClermidyCea-Leti, Grenoble, France, ―An Introduction to Multi--‐Core System on Chip – Trends and challenges‖
[3]. Phi-Hung Pham, Junyoung Song, Jongsun Park, and Chulwoo Kim, ―Design and Implementation of an On-Chip Permutation Network for Multiprocessor System-On-Chip‖ IEEE transactions on very large scale integration (VLSI) systems, vol. 21, no. 1, January 2013.
[4]. V.Prasanna Srinivasan, A.P.Shanthi, ―A Survey Of Research And Practices In Multiprocessor System On Chip Design Space Exploration‖,Journal of Theoretical and Applied Information Technology, Vol. 64 No.1, 10 June 2014