iosr-JVSP   Volume-6 ~ Issue-3 ~ May-June 2016

ABSTRACT: The study was conducted to evaluated prolong shelf-life effect of seventeen flavoring spices in Sudan local market, however, spices were different chemically in (protein, fat, ash, and moisture %). There were significantly different in pH value within the spices types and all in acidity rang (4.07 – 6.10) for cloves and ginger respectively. The microbial growth was assessed by total viable bacterial count for each one and there were significantly different......

[1]. Aberle, E.D., Forrest, J.C., Gerrard, D.E., Mills, E.W., Hedrick, H.B., Judge, M.D. & Merkel, R.A.(2001). Principles of Meat Science. Kendall Hunt Dubuque, lowa, pp.354.
[2]. Aneta Wojdyło a,*, Jan Oszmian´skia,Renata Czemerys.(2007). Antioxidant activity and phenolic compounds in 32 selected herbs. Food Chemistry 105(2007) 940–949
[3]. AOAC(1980). Official methods of analysis of the Association of Official Analytical Chemists (ed. W. Harwitz), 13th edition. Washington, D.C.
[4]. Beuchat, L.R.: Antimicrobial properties of spices and their essential oils, in Natural Antimicrobial Systems and Food Preservation. Eds. Y. M. Dillon and R. G. Board, CAB International, Oxon, (1994) pp. 167–179.
[5]. Brightwell, G., Clemens, R., Adam, K., Urlich, S., and Boerema, J. 2009. Comparison of culture-dependent and independent techniques for characterization of the microflora of peroxyacetic acid treated, vacuum-packaged beef. Food Microbiology, 26, 283-288.

ABSTRACT:The VLSI design is divided into different stages to reduce complexity. The physical design is one among the stages of VLSI design. It is also further classified into different phase to ease the physical design. Channel routing is one of the key areas in VLSI physical stage. The routing of channel problem is considered in the further discussion. The channel routing has many objectives such as reducing vias, minimizing length of wire and reduction of area utilized for routing.......

Keywords: Channel Routing, Clique, HCG, HNCG, VCG, Track

[1]. Sherwani N. A., "Algorithms for VLSI Physical DesignAutomation," Springer Private Limited, New Delhi, 1999.
[2]. A. Pal, T. N. Maldal, S. SahaSau, A. K. Dutta, R. K. Pal and A.Chaudhuri, "Graph – The Tool to Visualize the Problems in VLSI Channel Routing." Assam University Journal of Science & technology, Vol. 7, Number II, pp 73-83, 2011.
[3]. T. Yoshimura and E. S. Kuh, (1982) "Efficient Algorithms for Channel routing," IEEE Trans. On CAD of Integrated Circuits and Systems, vol. 1, pp. 25-35.
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ABSTRACT: Analog to Digital Converters (ADCs) & Digital to Analog Converters (DACs) are called mixed-signal designs. ADC and DAC are also called CODER and DECODER respectively or the CODEC. ADC and DAC are used either for data processing applications or signal processing applications. To design analog to digital converters of data processing applications the normal sampling rate is sufficient whereas for signal processing applications over sampling is necessary since the signal is to be reconstructed well at the output of the receiver. But, the over sample ADC like Sigma-Delta, is limited with the speed.......

Keywords: ADC; DAC; CODEC; Sigma-Delta; MAC; Mixed signal designs; Simulation tool.

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[4]. Taek-Jun Kwon, Jeff Sondeen, Jeff Draper USC Information Sciences Institute Design Trade-Offs institute "Floating-Point Unit Implementation for Embedded and Processing-In-Memory Systems" 4676 Admiralty Way Marina del Rey, CA 90292 U.S.A.
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ABSTRACT: Fruit classification is an emerging technique to classify the quality of fruits in large quantities. In this paper, we propose the design and implementation of citrus classification architecture on FPGA. The input color image is separated into R, G and B component and applied to Gaussian filter for smoothening of high frequency edges. The binarization technique is applied to smoothened image to obtain the limited range of representation to increase the visibility.......

Keywords: Pixel Classification, Citrus, Mean Filter, Binarization, Gaussian Filter etc.,

[1]. Marco Aurelio Nuno-Maganda, Cesar Torres-Huitzil and Josue Jimenez-Arteaga, "FPGA-based Real-Time Citrus Classification System",IEEE conference, 978-1-4799-2507-0/14/ 2014.
[2]. Meenu Dadwal, V.K.Banga," Estimate Ripeness Level of fruits Using RGB Color Space and Fuzzy Logic Technique", International Journal of Engineering and Advanced Technology (IJEAT) ISSN: 2249 – 8958, Volume-2, Issue-1, October 2012
[3]. Jagadeesh. D. Pujari, Rajesh. Yakkundimath, A. S. Byadgi," Reduced Color and Texture features based Identification and Classification of Affected and Normal fruits‟ images", International Journal of Agricultural and Food Science 2013, 3(3): 119-127
[4]. Chandinika D, Anitha U.," Novel Development of Sorting and Grading of Fruits from Colour Images Using Fuzzy Logic Technique", Research Journal of Pharmaceutical, Biological and Chemical Sciences, May – June 2015, 6(3) Page No. 876
[5]. Jaspinder Pal Singh," Designing an FPGA Synthesizable Computer Vision Algorithm to Detect the Greening of Potatoes", International Journal of Engineering Trends and Technology (IJETT) – Volume 8 Number 8- Feb 2014, Page 438

ABSTRACT: The main aim of this paper is to design and implement efficient UART and test the UART with built in self testing technique . A new Test pattern generator is simulated and used in BIST architecture in order to reduce power dissipation. As we know that power dissipation is more during the test mode than in normal mode hence In this project the pattern generator used is the low power pattern generator in order to reduce the power dissipation during test mode. The project is synthesized using Xilinx 14.5 design suite

Keywords: BIST,DFT,LP-LFSR, Test pattern generator, UART

[1] BalwinderSingh, Arun khosla and Sukhleen Bindra "Power Optimization of linear feedback shift register (LFSR) for low power BIST" , 2009 IEEE international Advance computing conference (IACC 2009) Patiala,India 6-7 March 2009.
[2] Y.Zorian, "A Distributed BIST control scheme for complex VLSI devices," Proc. VLSI Test Symp., P.4-9,1993
[3] P.Girard," survey of low-power testing of VLSI circuits," IEEE design and test of computers, Vol. 19, no.3,PP 80-90,May-June 2002
[4] P.Girard,L.Guiller,C.Landrault,S.Pravossoudovitch and H.J.Wunderlich," A modified clock scheme for a low power BIST test pattern generator," 19th IEEE proc. VLSI test Symp.,CA,pp-306- 311,Apr-May 2001.
[5] Mechrdad Nourani,"Low-transition test pattern generation for BIST- Based Applications", IEEE TRANSACTIONS ON COMPUTERS, Vol57,No.3 ,March 2008.

ABSTRACT: This paper introduces a brief description about Critical path realization of the Least Mean Square (LMS) adaptive filter and modified Delayed Least Mean Square (DLMS) adaptive filter to achieve a lower adaptation delay. To achieve lower adaptation delay, it is shown that the direct form LMS filter has longest critical path delay, to reduce the critical path delay pipelining implementation is required but conventional LMS adaptive filter does not support when it exceeds the desired sample period.......

Keywords: Adaptation Delay, Adaptive filter, Critical path, Delayed LMS adaptive filter, LMS adaptive filter.

[1]. B. Widrow and S. D. Stearns, Adaptive Signal Processing. Englewood Cliffs, NJ, USA: Prentice-Hall, 1985.
[2]. S. Haykin and B. Widrow, Least-Mean-Square Adaptive Filters .Hoboken, NJ, USA: Wiley-Inter science, 2003.
[3]. M. D.Meyer and D. P. Agrawal, "A modular pipelined implementation of a delayed LMS transversal adaptive filter," in Proc. IEEE Int. Symp. Circuits Syst., May 1990, pp. 1943–1946.
[4]. E. Mahfuz, C. Wang, and M. O. Ahmad, "A high-throughput DLMS adaptive algorithm," in Proc. IEEE Int. Symp. Circuits Syst., May 2005, pp. 3753–3756.
[5]. P. K.Meher and S. Y. Park, "Low adaptation-delay LMS adaptive filter Part-II: An optimized architecture," in Proc. IEEE Int. Midwest Symp. Circuits Syst., Aug. 2011.

ABSTRACT: Threshold Segmentation is an important image segmentation method and one of the most important preconditioning steps of image detection and recognition, and it has very extensive application on the research scopes of image processing and computer vision. Thresholding is one of the simplest approach to separate out the object from the background image.......

Keywords: Image Segmentation, OTSU Global Thresholding, Image Morphology, Histogram Analysis, Vessels Structure

[1]. Klein R, Klein B. Vision disorders in diabetes. In: National Diabetes Data Group, ed. Diabetes in America. 2nd ed. Bethesda, MD: National Institutes of Health, National Institute of Diabetes and Digestive and Kidney Diseases; 1995, pp. 293337.
[2]. Facey et al.,2002 ; Fransen et al., 2002; Hansen et al.,2004b ; Klein et al.,2004a ; van Leeuwen et al.,2003.
[3]. A Osareh,1 ,M Mirmehdi,1 B Thomas,1 and R Markham2 , (2003), Automatic Recognition of Exudative Maculopathy using Fuzzy C-means Clustering and Neural Networks, Department of Computer Science, University of Bristol, Bristol, BS8 1UB, U.K., Br J Ophthalmol 2003;87, Journal in Clinical science.:pgs: 1220-1223 doi:10.1136/bjo.87.10.1220.
[4]. Neera Singh, (2010), Automated Early Detection of Diabetic Retinopathy Using Image Analysis Techniques, International Journal of Computer Applications, Volume 8– No.2, pgs: 0975 – 8887.

ABSTRACT: With the continuously expanding of market for portable devices such as wireless communication devices, portable computers, consumer electronics and implantable medical devices, low pow- er is becoming increasingly important in integrated circuits. Also Mixed-signal designs are becoming more and more complex every day. In order to adapt to the new market requirements, a formal process for design and verification of mixed signal sys- tems i.e. top-down design and bottom-up verification methodolo- gy is required. This methodology has already been established for digital design.......

Keywords: ...................

[1]. VLSI Fabrication principles silicon and gallium Arsende
[2]. Second edition, Sorab .k.Ghandhi
[3]. The designers Guide to VHDL ,First edition, Peter.J.Absenden
[4]. Modern VLSI Design ,Sytem -on –Chip Design. Third edition, Wayne wolf. [4].http://www.wsts.org
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ABSTRACT: In this paper, AMBA AXI v1.0 is verified using UVM (Universal Verification Methodology) where verification environment is created. Verification is carried out by System Verilog language and UVM modelling approach. There are five independent channels in AXI and each channel is verified which includes write address, data and response channels and read address and data channels. Mentor Graphics Questa-Sim tool is used to perform the functional verification of AMBA AXI v1.0

Keywords: Verification IP; System Verilog; Transactions; Channels; Out of order transfer; UVM; Questa-Sim

[1]. Golla Mahesh, Sakthivel.S.M, Verification IP for an AMBA-AXI Protocol using System Verilog, International Journal of Engineering Research and General Science, Volume 3, Issue 1, January-February, 2015
[2]. Karthik Ghanta and Srikanth Parikibandla, Design of a Two-Way Set-Associative Cache, Advance in Electronic and Electric Engineering, Volume 3, Number, 2013 Research India Publications.
[3]. Mahendra.B.M, Ramachandra.A.C, Bus Functional Model Verification IP Development of AXI Protocol, International Journal of Engineering Research and General Science, Volume 3, special Issue 1, February, 2014
[4]. Anusha Ranga, L. Hari Venkatesh, Venkanna, Design and Implementation of AMBA-AXI Protocol Using VHDL for SOC Integration, International Journal of Engineering Research and General Science, Vol. 2, Issue4, July-August 2012
[5]. AMBA AXI Protocol Specification, ARM

ABSTRACT: This paper presents the implementation of RISC-V processor with low power optimization techniques. To minimize the power of the processor techniques as clock tree optimization and clock gating to reduce dynamic power along with Multi-Vth, Power Shut Off (PSO) and Multi Supply Voltage (MSV) to reduce leakage power are proposed. Synthesis is done using Encounter RTL Compiler to generate netlist at the gate level and the back end flow of VLSI design is carried out on Cadence Encounter Digital Implementation System using the power intent captured by the Common Power Format (CPF) which aid in the low power implementation the processor........

Keywords: RISC-V, Low Power, Clock Gating, Multi-Vth, Multi Supply Voltage, Power Shut Off, Common Power Format

[1] Leena Singh, Leonard Drucker and Neyaz Khan, A SystemC Based Approach for Successful Tapeout, Kluwer Academic Publishers, Norwell, MA, 2004
[2] Andrew Piziali, Functional Verification Coverage Measurement and Analysis,Kluwer Academic Publishers,Norwell, MA, 2004
[3] H. Menager, Low power specification and scalable approach to designing a complex SoC,Si2 LPC DAC 2007 workshop, June 3rd 2007.
[4] H. Menager, Words of Power: Reusable, Holistic, Scalable Multi-Voltage Design.EPD2007 Workshop, April 12th 2007.
[5] Hailin Jiang, Marek-Sadowska, M., Nassif,Santa Barbara, CA,USABenefits and costs of power-gating technique,Proc.IEEE International Conference2005.

ABSTRACT: This paper aims at developing a analysis and synthesis system for encoding great quality speech signal at a low bit rate and synthesizing the original speech signal . To execute this we have utilized extremely efficient method Linear Predictive Coding(LPC). It gives exact estimation of speech parameters. The encoding procedure of LPC includes estimation of speech parameters for demonstrating the vocal tract, which are useful in generation of synthesized speech signal by decoder. Voice excited LPC is developed and is compared with the plain LPC. The conclusion shows that this method encodes speech signal at a low bit rate with great quality and voice excited LPC gives output which is more intelligible than plain LPC.......

Keywords:Linear Predictive Coding, Levinson Durbin Recursion, Quantization, Autocorrelation.

[1]. L. R. Rabiner, R. W. Schafer, "Digital Processing of Speech Signals." Prentice Hall, Englewood Cliffs, New Jersey,
[2]. B. S. Atal, M. R. Schroeder, and V. Stover, "Voice- Excited Predictive Coding Systetm for Low Bit-Rate Transmission of Speech", Proc. ICC, pp.30-37 to 30-40
[3]. Landy Goldbarg and Lance Reik ," A practica handbook of Speech coding" chapter 4,1-4
[4]. K.Goyal, Multiple description coding compression meets the network, signal processing magazine, IEEE, vol 18 no5,pp 7493,2001.
[5]. W.Griffin and J.S.Lim(1998)multiband excitation vocoder, Acoustic, speech and signal processing, IEEE transactions on vol 36 no8,pp 1223-1235

ABSTRACT: As technology gets smaller, the processor chips become progressively more parallel and the task played by the communication system becomes more important. The communication system accounts for key section of the total thermal energy dissipation in terms of links. The link energy utilization is mainly due to switching activities involved. Hence we propose a set of data encoding schemes in this paper to triumph over these problems encountered. In this paper we also introduce an error detection scheme to check for any mismatches or errors in the encoding-decoding process.......

Keywords:Coupling Switching, data encoding, error detection, network on chip (NoC), power analysis

[1] Vittal and M. Marek-Sadowska"Crosstalk reduction for VLSI," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 16, no. 3, pp. 290–298, Mar. 1997.
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[3] S. Kavitha (2014), Data Encoding Technique Using Gray Code in Network-on-Chip, IJST, Vol. 2, 186-193.
[4] M. R. Stan and W. P. Burleson, "Bus-invert coding for low-power I/O," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 3, no. 1, pp. 49–58, Mar. 1995.
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ABSTRACT: Modern communication applications operating in Ultra High Frequency (UHF) band requires low phase noise, tight initial frequency calibration, good frequency stability over wide temperature range and low power consumption. All these parameters are achieved by the best sample of Temperature Compensated Crystal Oscillator (TCXO) only in 10-50MHz frequency band. It will be challenge in order to get these tighter specifications at VHF/UHF band.......

Keywords:Phase noise, PLL, TCXO, VCXO, Microcontroller, UHF band

[1] H. Meyer, G Ascheid, "Synchronisation in Digital Communications",vol-1, John Willey & Sons, 1990
[2] R.L. Best, Phase Locked Loops: Design, Simulation and Applications, 3rd edition, McGraw-Hill, 1997.
[3] S.Kandeepan, "Synchronisation Techniques for Digital Receivers", PhD Thesis, University of Technology Sydney, 2003
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ABSTRACT: This proposed paper presents architecture of generalized recursive function to generate approximation of orthogonal function DCT with an approximate length N could be derived from a pair of DCTs of length (N/2) at the cost of N additions for input preprocessing. Approximation of DCT is useful for reducing its computational complexity without impact on its coding performance. Most of the existing design for approximation of the DCT target only the small transform lengths DCT.......

Keywords:Algorithm-architecturecodesign, DCT approximation, discrete cosine transform, high efficiency video coding.

[1] A. M. Shams, A. Chidanandan,W. Pan, and M. A. Bayoumi, "NEDA: A low-power high-performance DCT architecture," IEEE Trans. Signal Process.,vol. 54, no. 3, pp. 955–964, 2006.
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[3] M. Jridi, P. K. Meher, and A. Alfalou, "Zero-quantised discrete cosine transform coefficients prediction technique for intra-frame video encoding," IET Image Process., vol. 7, no. 2, pp. 165–173, Mar. 2013.
[4] S. Bouguezel, M. O. Ahmad, and M. N. S. Swamy, "Binary discrete cosine and Hartley transforms," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 60, no. 4, pp. 989–1002, Apr. 2013.
[5] F. M. Bayer and R. J. Cintra, "DCT-like transform for image compression requires 14 additions only," Electron. Lett., vol. 48, no. 15, pp. 919–921, Jul. 2012

ABSTRACT: Design of reducing area, high speed and power are the major areas in VLSI system design. In this design parallel prefix adders are designed such as Kogge-stone adder, Breunt-Kung adder, Ladner-Fischer adder .Radix-4 Booth multiplier is designed by using Kogge-Stone adder. Vedic multiplier and Vedic division is used to reduced area, LUT tables and increase the speed. The design is synthesized using Xilinx ISE 10.1 design suite and done Cadence Encounter........

Keywords:Prefix adders, Vedic multiplier, Vedic division, Radix-4 Modified Booth Multipler

[1] Young-Ho Seo and Dong-Wook Kim, A New VLSI Architevture of parallel Multiplier-Accumulator based on Radix-2 Modified Booth Algorithm. IEEE Trans.vol.18.No.2 FEB 2010.
[2] Information Technology-Coding of Moving Picture and Associated Autio, MPEG-2 Draft International Standard, ISO/IEC 13818-1,2, 3,1994.
[3] Sengupta, Sultana and Chaudhuri, "An algorithm facilitating fast BCD division on low end processors using Ancient Indian Vedic Mathematics Sutras," Proceedings of International Conference on Communications,Devices and Intelligent Systems, 2012, pp. 373-376.
[4] B. R. Appasaheb and V S Kanchana Bhaaskaran, "Design and implementation of an efficient multiplier using vedic mathematics and charge recovery logic," Proceeding of International Conf. on VLSI,

ABSTRACT: Filters are broadly utilized as a part of communication and signal processing systems. At times, reliability becomes critical for such systems and fault tolerant usages are required. Over a long time, numerous procedures have been proposed that makes full use of filters structure and properties to accomplish fault tolerance. In certain complex systems, it is commonly found that filters work in parallel. For instance, by applying the same filter to various information signals.......

Keywords:Error Correction Codes (ECCs), Filters, and multiple bits.

[1] M. Nicholaidis, "Design for soft error mitigation," IEEE Trans. Device Mater. Rel., vol. 5, no. 3, pp. 405-418, Sep. 2005.
[2] A. Reddy and P. Banarjee "Algorithm-based fault detection for signal processing applications," IEEE Trans Comput,. vol.39, no 10, pp. 1304-1308, Oct. 1990.
[3] B. Shim and N. Shanbhag, "Energy-efficient soft error-tolerant digital signal processing," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 14, no. 4, pp. 336-348, Apr. 2006.
[4] T. Hitana and A. K. Deb, "Bridging concurrent and non-concurrent error detection in FIR filters," in Proc. Norchip Conf., 2004, pp. 75-78.
[5] S. Pontarelli, G. C. Cardarilli, M. Re, and A. Salsano, "Totally fault tolerant RNS based FIR filters," in Proc. IEEE IOLTS, Jul. 2008. pp. 192-194.

ABSTRACT: The basis of numerous operations such as counting, multiplication, filtering are done with the full adder. Adders are heart of computational circuits and many compound arithmetic circuits on the basis of addition. The vast uses of this operation in arithmetic functions attract a lot of researcher's attention for mobile applications. Nowadays, various adder implementations are available in order to realize the speed or density requirements in which adder's optimization is paramount factor. This paper describes GDI based XNOR logic 4-bit full adder......

Keywords: Full Adder, GDI (Gate Diffusion Input), Sleep Transistor

[1] I-Chyn Wey, Chun-Hua Huang, and Hwang-Cherng Chow, "A New Low-Voltage CMOS 1-Bit Full Adder for High Performance Applications", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2002
[2] Arkadiy Morgenshtein, Alexander Fish, and Israel A. Wanger, "Gate-Diffusion Input (GDI): A Power- Efficient Method for Digital Combinatorial Circuits", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.-10, no.-5, pp. 566-581, October 2002
[3] Lekshmi Vijayan, Sukanya Sundaresh, "Ground Bounce Noise Reduction Using Power Gating Techniques", International Journal of Scientific Engineering and Research(IJSER), Vol.-2 Issue 7, pp.20-26, July 2014
[4] Soolmaz Abbasalizadeh and Behjat Forouzandeh, "Full Adder Design with GDI Cell and Independent Double Gate Transistor", 20th Iranian Conference on Electrical Engineering,(ICEE2012), pp.130-134, May 15-17,2012, Tehran, Iran

ABSTRACT: Image Compression is basically defined as reducing the size of image without altering the picture quality of the original image. Various algorithms are currently available for compression of the images, among them the most prominent algorithms the wavelet transform. In recent technology Wavelet transform is named as cutting-edge technology for image processing applications. Discrete cosine transform (DCT) was previously used to compress the image.......

Keywords: CDF, DWT, LUT, DCT etc.,

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[2]. Durgasowjanya, K.N.H. Srinivas and P. VenkataGanapathi,"FPGA Implementation of efficient VLSI Architecture for fixed point1-D DWT using Lifting Scheme", International Journal of VLSI Design and Communication Systems, Vol. 3, No. 4, 2012.
[3]. Nagabushanam M and Ramachandran S., "Fast implementation of Lifting Based 1D/2D/3D DWT-IDWT Architecture for Image Compression", International journal of computer Applications, Vol. 12, Issue. 11, pp. 23-29, 2012.
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ABSTRACT: This paper presents the implementation of a proportional-integral-Derivative (PID) controller for motion control of a DC motor based on FPGA. This implementation technique used to avoid the problems which create during analog and digital interfacing system in real-time.the controller used in speed controller loop. The hardware implementation has been done on a Xilinx Spartan 3 FPGA chip and generates the PWM signal as an input of motor driver for controlling. The out of optically encoded data is decoded and give it to PID control loop. Proposed implementation is present through the VHDL algorithm

Keywords: PID controller, USB-6008, DC motor, FPGA, Xilinx Spartan 3.

[1]. Somsubhra Ghosh1,Ranjit kumar Barai2,samar Bhattarcharya,prathana Battarcharya3,ShubhobrataRudra4,Arka Dutta5,Rownick Pyne6,"An FPGA Based Implementation of a Flexible Digital PID Controller For a Motion Control System,"2013 International Conference on Computer Communication and Informatics (ICCCI-2013),jan.09-11,2013.
[2]. Y.-Y. Tzou, T.-S. Kuo, "Design and Implementation of an FPGA-BasedMotor Control IC," in Proceesings of IEEE IECON 1997, vol. 2, pp.943-947.
[3]. L. F. Castano, G. A. Osorio, "Design of a FPGA based position PI servo controller for a DC motor with dry friction," in Proceedings of IEEE VII Southern Conference on Programmable Logic, pp. 75-80, 2011.
[4]. Y.-S. Kung, P.-G. Huang, C.-W. Chen, "Development of a SOPC for PMSM drives," in Proceedings of 47th IEEE International Midwest Symposium on Circuits and Systems, vol. 2, pp. II-329-II-332, 2004.